PCIe Transfer Timing for Lower-Power Computing Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computing devices, particularly mobile devices, face challenges in balancing power consumption with increased data processing demands due to higher data rates, leading to excessive power consumption and reduced battery life, especially with PCIe and USB 3.0 buses.
Innovation Solution
Implementing timers and counters to synchronize and accumulate data transfers on PCIe buses, reducing unnecessary transitions between power states by holding data until predefined conditions are met, such as timer expiration or threshold limits, to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCIe or USB 3.0 buses are used to handle high data rates, then data processing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using timers to control when data transfers occur on the PCIe bus. Instead of continuous data transmission, the system uses downlink timers and uplink timers to create periodic transfer windows, allowing the bus to enter low-power states between transfers. This reduces overall power consumption while maintaining the ability to handle high data rates when needed.
Solution Approach 2:
The patent applies preliminary action by accumulating data in buffers before triggering PCIe transfers. Data is held in accumulation buffers until sufficient data is available or a timer expires, then a single consolidated transfer is initiated. This prevents multiple small transfers that would keep the bus in high-power state frequently, thereby reducing power consumption while maintaining high data rate capability.
2Productivity
If data is transferred immediately when available, then data processing speed is improved, but unnecessary power state transitions occur
Solution Approach 1:
The patent merges multiple data transfers into single consolidated transfers by accumulating data in buffers until a timer expires or a threshold is reached. Instead of transferring data immediately when each packet arrives, the system combines multiple packets into one transfer operation, reducing the number of power state transitions on the PCIe bus while maintaining data processing throughput.
Solution Approach 2:
The system performs preliminary data accumulation in buffers before initiating PCIe transfers. Data is held in accumulation buffers with associated timers, and transfers are triggered only when accumulation conditions are met. This preliminary accumulation phase allows the system to consolidate multiple small transfers into fewer larger transfers, reducing power state transitions while maintaining overall data processing speed.
Data Source
AI summary
Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.