PCIe Universal Routing ID Expands Addressable Device Count
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Solution Overview
Problem
The PCI Express (PCIe) architecture is limited by the number of devices it can support due to its point-to-point connection structure, which restricts the number of devices that can exist in a PCI subsystem, and existing solutions like non-transparent bridges and alternative routing interpretation do not effectively increase the number of supported devices.
Innovation Solution
The introduction of a Universal Routing ID (URID) scheme, which expands the 16-bit BDF to enable 64K addressable functions, allowing tens of thousands of single-function devices to be connected to the PCIe fabric by redefining the routing identifier and adding a URID capability segment in the PCIe packet configuration space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If point-to-point connection structure is used in PCIe architecture, then communication speed is improved, but the number of supported devices is limited
Solution Approach 1:
The patent extends the routing identifier from the traditional 16-bit BDF format to a 32-bit URID format, adding an extra dimension to the addressing space. This allows the system to maintain point-to-point high-speed communication while dramatically increasing the number of addressable devices from 256 to over 4 billion devices.
Solution Approach 2:
The patent changes the parameter of routing identifier width from 16 bits to 32 bits, fundamentally altering the addressing capability. This parameter change enables the system to support a vastly expanded number of devices while preserving the high-speed point-to-point communication characteristics of PCIe.
2Quantity of substance
If Universal Routing ID scheme is introduced to expand routing capabilities, then the number of supported devices is increased, but system complexity increases
Solution Approach 1:
The patent implements preliminary action by having the Root Complex automatically generate and assign URIDs to devices during the device enumeration process. This eliminates the need for manual routing configuration and reduces system complexity by automating what would otherwise be a complex manual setup process.
Solution Approach 2:
The patent enables self-service by allowing devices to automatically receive and configure their own URIDs through the enumeration process. The system handles routing identifier assignment autonomously without requiring user intervention or complex manual configuration, thereby reducing overall system complexity despite the expanded routing capabilities.
3Adaptability or versatility
If existing PCI bus structure is maintained for software compatibility, then software compatibility is preserved, but the number of supported devices is severely limited
Solution Approach 1:
The patent achieves universality by designing a system where the same PCIe physical layer and point-to-point connection structure serve dual purposes: maintaining compatibility with existing PCI software protocols while simultaneously enabling support for a vastly expanded number of devices through the enhanced URID routing mechanism.
Data Source
AI summary
A universal routing identifier (URID) is provided to extend the function space in PCI-Express fabrics. Methods and systems based on the URID are provided for configuring URID capable devices and upgrading PCI-Express bridges and switches having lookup tables with access control functionality. The lookup table entry contains URIDs of destination ports, backup ports, acceptance ports, and permitted ports for downstream and upstream filtering, routing and arbitrating of transaction packets. URID capable devices can be incrementally added to current PCI-Express bridges and switches. A configuration mechanism is added to the current PCI/PCI-Express enumeration software. The URID capabilities can be disabled to maintain system compatibility. A URID capable PCI-Express system is able to address ten of thousands single-function devices. A URID capability segment field is provided in the current PCI-Express configuration space. Each URID capable device contains the URID capability segment implemented in its own set of configuration space registers.