Multi-Lane PCI-E to USB 3.0 Bridge Bandwidth Distribution
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Solution Overview
Problem
The existing bridges between PCI-E and USB 3.0 devices are limited by a single lane's 5 Gbps data transmission speed, restricting the total data transmission speed when multiple USB 3.0 devices are coupled, resulting in each device achieving less than 5 Gbps.
Innovation Solution
A bridge with a PCI-E interface supporting at least two lanes and a USB 3.0 root hub with two controllers, allowing each USB 3.0 device to achieve up to 5 Gbps data transmission speed by distributing the total bandwidth across multiple lanes and controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single lane PCI-E interface is used to connect multiple USB 3.0 devices, then the bridge structure is simple, but the data transmission speed of each USB 3.0 device is limited to less than 5 Gbps
Solution Approach 1:
The patent segments the data transmission path by introducing multiple lanes (first lane and second lane) in the PCI-E interface, each capable of independently transmitting data at 5 Gbps. This segmentation allows the total bandwidth to be divided among multiple USB 3.0 devices while maintaining high speed for each device, resolving the contradiction between simple structure and high transmission speed.
2Adaptability or versatility
If multiple USB 3.0 devices are coupled to a single lane bridge, then the device connectivity is increased, but the sum of data transmission speeds is limited to 5 Gbps
Solution Approach 1:
The patent transitions from a single-dimensional data transmission path (one lane) to a multi-dimensional path by adding a second lane. This dimensional expansion allows the system to simultaneously support multiple USB 3.0 devices at 5 Gbps each, increasing both device connectivity and total transmission capacity beyond the original 5 Gbps limit.
3Speed
If a PCI-E interface with multiple lanes is used, then the data transmission speed can be increased, but the device complexity and cost increase
Solution Approach 1:
The patent designs the bridge to support multiple USB 3.0 devices through a universal multi-lane PCI-E interface structure. The same bridge architecture can accommodate different numbers and types of USB devices, providing flexibility and multi-functionality while maintaining high data transmission speeds, thus justifying the increased structural complexity through enhanced versatility.
Data Source
AI summary
A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.