PCIe Virtual Channel Traffic Prioritization Deadlock Prevention

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Solution Overview

Problem

The use of a single virtual channel in PCIe interfaces can lead to communication deadlocks between a CPU and a GPU due to ordering rules, which restrict traffic flow and prevent the GPU from accessing main memory until CPU requests are satisfied, a situation that cannot be resolved by operating systems limiting communication to a single virtual channel.

Innovation Solution

Implementing traffic prioritization via traffic classes and credit/tag reservation to create multiple effective channels over a single virtual channel, allowing packets to pass based on their traffic class, and dynamically managing credits and tags to prevent overloading and enable fine-tuned communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single virtual channel is used for PCIe communication, then the system simplifies the communication interface, but it causes communication deadlock between CPU and GPU due to ordering rules

Engineering Contradiction:
Improvecommunication interface complexityVSAvoidcommunication deadlock prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the single virtual channel into multiple traffic classes (e.g., priority and non-priority classes). Each traffic class is assigned separate credit pools and tag pools, effectively creating multiple logical channels within a single physical virtual channel. This segmentation allows different types of traffic to be managed independently, preventing deadlock by ensuring that high-priority traffic can proceed even when low-priority traffic is blocked.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of differentiation within the single virtual channel by using traffic class priority levels. Instead of adding multiple physical virtual channels (spatial dimension), it creates hierarchy levels within the existing channel (temporal/priority dimension). Packets are tagged with priority indicators that allow the system to arbitrate access based on priority, effectively adding a temporal ordering dimension to the communication flow.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple virtual channels are used for PCIe communication, then communication deadlock is prevented, but the operating system cannot utilize them due to single virtual channel limitation

Engineering Contradiction:
Improvecommunication deadlock preventionVSAvoidoperating system compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent makes the single virtual channel universal by enabling it to handle multiple traffic classes simultaneously. The hardware layer (PCIe interface and chipset) is enhanced to support multi-class traffic arbitration, credit management, and tag routing within a single virtual channel. This allows the system to provide multi-channel functionality at the hardware level while maintaining single-channel compatibility at the software/OS level, achieving both deadlock prevention and operating system compatibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces traffic class arbitration mechanisms and credit/tag management systems as intermediaries between the physical PCIe interface and the operating system. These intermediaries translate the OS's single virtual channel requests into multiple prioritized traffic streams, managing the complexity of multi-class handling without requiring OS awareness or modification.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If traffic prioritization and credit/tag reservation are implemented, then deadlock is prevented and communication performance is improved, but the system complexity increases

Engineering Contradiction:
Improvecommunication performanceVSAvoidtraffic management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-allocating credit pools and tag pools to different traffic classes before communication begins. Each traffic class is assigned a reserved portion of available credits and tags, establishing priority and resource guarantees in advance. This pre-configuration simplifies runtime arbitration, as the system only needs to check pre-established allocations rather than making complex decisions for each packet, thereby improving performance while managing complexity through upfront planning.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8532098B2System and method for virtual channel communication
Publication Date: 2013.09.10 NVIDIA CORP
  • US8532098B2 patent drawing
  • US8532098B2 patent drawing
  • US8532098B2 patent drawing

AI summary

A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.