PCIe Virtual Channel Routing for CPU Read Deadlock Avoidance
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Solution Overview
Problem
Deadlocks occur in computer systems when the CPU and PPU are connected by a PCIe bus with pending write requests, preventing read completions from passing write requests and halting communication, which negatively affects processing throughput.
Innovation Solution
A method and system that route read completions through a secondary virtual channel of the PCIe bus, avoiding deadlocks by marking requests from the CPU as 'special' and transmitting derivative read requests on a separate virtual channel, ensuring read completions can reach the PPU without being impeded by pending write requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If read completions are transmitted on the same PCIe bus channel as write requests, then the PCIe bus structure is simple, but deadlocks occur when write requests are pending and read completions cannot pass through
Solution Approach 1:
The PCIe bus is segmented into multiple virtual channels (VC0, VC1, etc.), allowing read completions and write requests to be transmitted on separate channels. This segmentation prevents deadlocks by enabling read completions to bypass pending write requests, while maintaining the overall simplicity of the PCIe bus structure through logical rather than physical separation.
Solution Approach 2:
Virtual channels act as intermediaries between read completions and write requests on the PCIe bus. By introducing this intermediary layer, the system allows read completions to be routed around blocked write requests, preventing deadlock conditions while maintaining the unified PCIe bus architecture.
2Device complexity
If derivative read requests are transmitted on the same virtual channel as CPU requests, then the virtual channel management is simple, but read completions may be blocked by pending write requests causing deadlocks
Solution Approach 1:
The system segments traffic into different virtual channels based on request type and origin. CPU requests use one virtual channel while derivative read requests use another, allowing read completions to bypass blocked write requests. This segmentation prevents deadlocks while keeping virtual channel management organized through clear traffic classification rules.
3Productivity
If the PPU processes write requests from the CPU, then processing throughput is improved, but deadlocks occur when the PPU needs to issue read requests that cannot return completions due to pending write requests on the PCIe bus
Solution Approach 1:
The patent introduces a special virtual channel as an intermediary for derivative read requests generated by the PPU. This intermediary channel allows read completions to return to the PPU even when regular PCIe channels are blocked by pending write requests, preventing deadlocks while maintaining high processing throughput.
Solution Approach 2:
The system dynamically selects virtual channels based on the type of request and current bus conditions. When write requests are pending on the PCIe bus, derivative read requests are automatically routed through alternative virtual channels, allowing the system to adapt to blocking conditions and prevent deadlocks while maintaining processing throughput.
Data Source
AI summary
Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.