Multiple PCIe Interfaces With Virtual Channels for Deadlock Avoidance
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Solution Overview
Problem
Integrated circuits face challenges with packet overflow and routing congestion due to increasing bandwidth demands in high-speed data transfers, particularly in PCIe communications, leading to potential data loss and system instability.
Innovation Solution
Implementing multiple independent streams with credit checks in integrated circuits for both receivers and transmitters to manage packet flow, dynamically allocating credits based on congestion patterns and throughput requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PCIe interfaces share a common buffer pool, then resource utilization is improved, but routing congestion and deadlock risk increase
Solution Approach 1:
The patent segments the routing space by implementing separate virtual channels for different packet types (posted, non-posted, completion packets). Each virtual channel operates independently with its own flow control, preventing congestion in one channel from blocking other channels. This segmentation resolves the deadlock issue while maintaining buffer sharing benefits.
Solution Approach 2:
The patent introduces virtual channels as intermediary layers between the PCIe interfaces and the buffer pool. These virtual channels act as mediators that manage packet flow and prevent direct conflicts between multiple interfaces accessing shared buffers, thereby reducing routing complexity while enabling buffer sharing.
2Ease of manufacture
If static routing techniques are used, then implementation simplicity is improved, but routing congestion increases
Solution Approach 1:
The patent implements dynamic routing through virtual channels that can adaptively handle different packet types. Instead of fixed static routing, the system dynamically assigns packets to appropriate virtual channels based on packet type and buffer availability, improving throughput while maintaining reasonable implementation complexity through standardized channel management.
Solution Approach 2:
The patent changes the routing parameter from fixed destination-based routing to flow-type-based routing. By categorizing packets into different flow types (posted, non-posted, completion) and routing them through dedicated virtual channels, the system improves throughput by preventing congestion propagation while keeping the routing logic manageable through parameter-based classification.
3Reliability
If packet buffering capacity is increased, then packet overflow is reduced, but memory bandwidth consumption increases
Solution Approach 1:
The patent applies partial buffering by implementing separate smaller buffer pools for each virtual channel instead of one large shared buffer. Each channel maintains just enough buffering capacity for its specific packet type, preventing overflow through distributed buffering while reducing total memory bandwidth consumption compared to a single large buffer serving all interfaces.
Solution Approach 2:
The patent segments the buffer pool into separate buffers for different packet types and virtual channels. This segmentation allows each buffer to be independently managed and sized appropriately for its traffic pattern, preventing overflow in any single channel without requiring excessive total buffering capacity across all interfaces.
Data Source
AI summary
Systems, methods, and circuitry for supporting high speed data transfers across link partners that are coupled by a communication link, such as a Peripheral Component Interconnect Express (PCIe). More specifically, integrated circuits, such as field programmable gate arrays (FPGAs), in a receiver may include multiple streams that are coupled to an application main band to improve the throughput of buffering and providing received packets to an application. The multiple streams may be first in, first out (FIFO) buffers that include a credit check to limit the risk of packet overflow. In some embodiments, integrated circuits in a transmitter may include multiple streams that are coupled to transmission processing circuitry. The transmitter may include a dynamic credit allocation system that adjusts credit allocations among the streams based on credit consumption data and congestion metrics.