Phase Change Memory Thermal Disturbance Control via Bank Segmentation
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Solution Overview
Problem
Phase change memory devices face issues with adjacent memory cells being disturbed due to heat from set or reset operations, leading to unintended changes in resistance values and data loss.
Innovation Solution
A semiconductor memory device with temperature sensors and a control logic block that manages the heating process by monitoring temperatures and preventing successive set or reset operations on memory cells if they exceed a threshold, thereby minimizing thermal disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If set or reset operations are performed on phase change memory cells, then resistance values of the memory cells are changed, but adjacent memory cells are heated and disturbed causing unintended resistance changes
Solution Approach 1:
The memory device is divided into multiple banks (first bank, second bank, etc.) with separate temperature sensors for each bank. This segmentation allows independent temperature monitoring and control for each bank, enabling precise management of thermal effects without affecting other banks. The control logic block can selectively inhibit operations in specific banks based on their temperature status while allowing operations in other banks.
Solution Approach 2:
Temperature sensors continuously monitor the temperature in each bank and provide feedback to the control logic block. Based on this feedback, the control logic block determines whether to permit or inhibit set/reset operations in each bank. This closed-loop feedback mechanism ensures that operations are only performed when temperature conditions are safe, preventing thermal disturbance to adjacent cells while maintaining manufacturing precision.
2Reliability
If temperature monitoring and control is implemented to prevent thermal disturbance, then data integrity is improved, but device complexity increases due to additional sensors and control logic
Solution Approach 1:
The temperature sensor and control logic block are integrated within the memory device structure itself rather than being external components. The control logic block is merged with the existing memory control architecture, combining temperature monitoring functions with standard memory control operations. This merging approach improves reliability through comprehensive temperature management while minimizing the increase in device complexity by reusing existing control infrastructure.
Solution Approach 2:
The memory device performs self-monitoring and self-control of temperature conditions through integrated sensors and control logic. The device automatically detects temperature changes and independently decides whether to permit or inhibit operations without requiring external intervention. This self-service approach enhances data integrity while keeping the device structure relatively simple by eliminating the need for external temperature management systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents data loss by ensuring that memory cells are not excessively heated, maintaining accurate resistance values and data integrity through controlled access operations.
Implementation Method 1
a sensor disposed adjacent to the banks and configured to sense a temperature
Implementation Method 2
the phase change memory, which is one of the nonvolatile memories, is configured to change resistance values of memory cells through heating of the memory cells
Implementation Method 3
when a set or reset operation is performed on a phase change memory, the memory cells of the phase change memory may be heated
Data Source
AI summary
A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.