Mitigating Bias Drift in Phase Change Memory Cells
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Solution Overview
Problem
Non-volatile memory devices, particularly phase change memory (PCM) with chalcogenide-based cells, face reliability issues due to bias-accelerated drift, leading to increased bit error rates and performance degradation over time, as sub-threshold bias voltages cause threshold voltage shifts and reduce the read-window margin.
Innovation Solution
Implementing a C-cell bias voltage on de-selected memory cells during write operations, specifically applying an additional positive voltage on unselected word-lines to mitigate bias-accelerated drift, which reduces the differential voltage bias and minimizes the impact of sub-threshold voltage pulses, thereby maintaining a larger read margin and reducing bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sub-threshold bias voltages are applied to de-selected memory cells during write operations, then write operation speed is improved, but threshold voltage drift increases and read margin is reduced
Solution Approach 1:
The patent applies a preliminary counteracting voltage (third bias voltage) to the second word-line before the harmful sub-threshold bias voltage fully affects the de-selected memory cell. This third bias voltage is specifically designed to offset the threshold voltage drift caused by the second bias voltage, thereby preventing read margin degradation while allowing fast write operations to proceed
2Reliability
If additional C-cell bias voltage is applied to mitigate bias drift, then read margin is maintained, but voltage overhead increases
Solution Approach 1:
The patent applies the third bias voltage selectively only to de-selected memory cells on the same bit-line as the selected cell, rather than uniformly to all memory cells. This localized application of counteracting voltage maintains read margin for affected cells while minimizing unnecessary voltage overhead on cells that do not require protection
3Reliability
If periodic refresh operations are performed to correct drift, then bit error rate is reduced, but system productivity decreases
Solution Approach 1:
The patent implements preliminary protection by applying the third bias voltage during normal write operations to prevent threshold voltage drift before it occurs. This proactive approach eliminates the need for subsequent periodic refresh operations to correct drift, thereby maintaining high system productivity while ensuring data integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces read margin loss, from approximately 150 mV at 1,000,000 bias cycles without C-cell bias voltage to 75 mV with its application, leading to fewer bit errors and reduced need for read retries, thus enhancing system performance while maintaining acceptable voltage overhead.
Implementation Method 1
A type of non-volatile memory architecture that may include phase change memory (PCM) may be susceptible to bias-accelerated drift
Implementation Method 2
Drift may be an activated process that may be accelerated over time by temperature or through electric field (e.g., sub-threshold bias voltage across a memory cell)
Data Source
AI summary
Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.