Phase Change Memory Block Stress Trim for Cell Variation
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Solution Overview
Problem
Phase change memory devices face cell-to-cell variations during manufacturing and operation, leading to reduced operating speed and data density, as well as decreased reliability, especially in multi-level cell operations.
Innovation Solution
A memory circuit with a controller that executes tailored program sequences and stress sequences on a block-by-block basis, using statistics to monitor performance and apply stress operations to alter cell characteristics, thereby improving operating speed and data density and reducing cell-to-cell variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard program operations are used for all memory blocks, then manufacturing simplicity is maintained, but cell-to-cell variations increase and operating speed decreases
Solution Approach 1:
The memory array is divided into multiple blocks, and each block is further segmented into groups of memory cells. Different program operations are applied to different blocks based on their specific performance characteristics, allowing tailored optimization for each segment while maintaining overall system manageability.
Solution Approach 2:
The patent applies local quality by assigning different program operations (with varying numbers of program pulses, verify thresholds, and pulse magnitudes) to different blocks based on their measured performance characteristics. This ensures that each block receives the appropriate level of programming effort tailored to its specific cell-to-cell variation profile.
2Productivity
If tailored program operations are applied to each block, then operating speed and data density improve, but device complexity increases
Solution Approach 1:
The controller performs preliminary characterization of each block's performance characteristics during manufacturing or initial operation. Based on these pre-determined characteristics, the controller selects appropriate program operations from a library of predefined patterns, avoiding the need for complex real-time adjustments during normal operation.
Solution Approach 2:
The patent varies multiple parameters of the program operations including the number of program pulses, verify thresholds, pulse magnitudes, and pulse widths. By adjusting these parameters based on block-specific characteristics, the system optimizes programming speed and reliability without requiring fundamentally different hardware architectures.
3Reliability
If more verify cycles are performed to accommodate cell variations, then reliability improves, but operating speed decreases
Solution Approach 1:
The verify cycle structure is made dynamic and adaptive rather than static. The number of verify cycles, the thresholds used for verification, and the program pulse characteristics are adjusted dynamically based on the block's measured performance characteristics. This allows the system to use fewer verify cycles for blocks with low variation and more verify cycles for blocks with high variation, optimizing both speed and reliability.
4Reliability
If cell-to-cell variations are reduced through manufacturing improvements, then reliability improves, but manufacturing cost and complexity increase
Solution Approach 1:
The system performs self-characterization and self-optimization by automatically measuring the performance characteristics of each block and selecting appropriate program operations without requiring external intervention or complex manufacturing processes. This shifts the optimization burden from the manufacturing stage to the operation stage, maintaining manufacturing simplicity while achieving high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the operating speed and data density of phase change memory devices by tailoring program operations to individual block performance characteristics, reducing cell-to-cell variations and improving reliability through wear leveling, hot and cold data allocation, and self-healing mechanisms.
Implementation Method 1
a stress sequence including a plurality of stress pulses is executed on a selected block of memory cells... the stress sequence includes stress pulses configured to stress memory cells in the block that do not pass verify
Implementation Method 2
The phase change memory element is made of phase change materials that exhibit a large resistivity contrast between crystalline (low resistivity) and amorphous (high resistivity) phases
Implementation Method 3
an electrical current pulse with a large magnitude for a short time period can be used to heat up an active region of the memory element to a melting temperature
Data Source
AI summary
A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.