Phase Change Memory Burst Write Partitioning
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Solution Overview
Problem
Phase change memory devices experience significant burst write latency due to asymmetric state change characteristics, where transitioning from the crystalline to the amorphous state is slower than vice versa, affecting data throughput in burst mode operations.
Innovation Solution
Implementing a dedicated burst write partition where memory cells are pre-conditioned into a low resistance crystalline SET state in background operations, followed by faster RESET state transitions for selected cells during burst write operations, thereby reducing latency by utilizing the faster RESET state transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional phase change memory write operations are used, then data can be written to memory cells, but burst write latency is significant due to asymmetric state change characteristics
Solution Approach 1:
The patent applies preliminary action by pre-conditioning memory cells into the crystalline state before burst write operations. Background operations prepare a dedicated partition of memory cells in the crystalline state, so that when burst write operations need to write to these cells, the cells are already in the optimal state for fast RESET transitions, eliminating the need to wait for state change during the burst write operation.
Solution Approach 2:
The patent segments the memory array into a dedicated burst write partition and other memory regions. This dedicated partition is specifically optimized for burst write operations and is maintained in the crystalline state through background operations, while other regions can be used for conventional operations. This segmentation allows the system to optimize performance for burst writes without compromising other memory operations.
2Speed
If SET state transitions are used for writing, then memory cells can be programmed, but the process is slower compared to RESET state transitions
Solution Approach 1:
The patent inverts the conventional write approach by using RESET transitions instead of SET transitions for writing to the dedicated burst write partition. Instead of transitioning from amorphous to crystalline state (SET), the system transitions from crystalline to amorphous state (RESET), which is inherently faster according to the asymmetric state change characteristics of phase change memory.
Solution Approach 2:
The patent changes the operational parameters by maintaining memory cells in the crystalline state rather than the amorphous state, and by using RESET transitions instead of SET transitions. This parameter change exploits the asymmetric state change characteristics to achieve faster write speeds in the dedicated burst write partition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces burst write latency by up to a factor of eight and improves memory programming bandwidth in burst write mode by leveraging the faster RESET state transition, enhancing overall data transfer efficiency.
Implementation Method 1
a state transition from the crystalline state (a high current, low resistivity state) to the amorphous state (a low current, high resistivity state relative to the crystalline state)
Data Source
AI summary
A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.