PCM Cache Architecture Using Drift CAM Pointers
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Solution Overview
Problem
The challenge in managing phase change memory cells lies in the resistivity drift phenomenon, which makes it difficult to determine a clear demarcation voltage for reading, leading to read errors, especially shortly after data is written, and results in overhead costs due to the need for separate memory structures like a drift buffer and media manager cache.
Innovation Solution
The implementation of a drift buffer is replaced by using pointers in a drift content-addressable memory (CAM) that references entries in the media manager cache, eliminating the need for a separate drift buffer and reducing overhead by avoiding unnecessary data movement and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate drift buffer is used to store data from phase change memory cells, then read errors due to resistivity drift are reduced, but device complexity and overhead costs increase
Solution Approach 1:
The patent merges the drift buffer and media manager cache into a single unified cache structure. The drift buffer is integrated as part of the media manager cache, eliminating the need for separate memory structures. This integration maintains the ability to handle resistivity drift while reducing overall system complexity and overhead costs.
Solution Approach 2:
The unified cache structure serves multiple functions: it acts as both a drift buffer for handling resistivity drift in phase change memory cells and a media manager cache for general data caching operations. This multi-functionality eliminates the need for separate specialized structures while maintaining all necessary capabilities.
2Reliability
If data is moved to a separate drift buffer shortly after writing, then read errors are avoided, but data movement overhead and access time increase
Solution Approach 1:
By integrating the drift buffer within the media manager cache rather than using a separate structure, data remains in a single location. This eliminates the need for physical data movement between separate buffers, reducing access time overhead while still providing drift compensation capabilities through the unified cache management.
3Reliability
If clear demarcation voltages are established for reading phase change memory cells, then read errors are reduced, but the system must accommodate the tails of the transition latency distribution which erodes performance value
Solution Approach 1:
The unified cache structure performs preliminary data storage and management, allowing the system to establish clear demarcation voltages for reading phase change memory cells. By pre-storing data in the unified cache and managing it there, the system can accommodate the tails of the transition latency distribution without eroding overall performance, as the cache provides a buffer that decouples the memory cell transition timing from the read operation timing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overhead costs and improves read efficiency by allowing data to remain in the media manager cache with pointers in the drift CAM, minimizing data movement and eliminating a separate memory structure, thus addressing the resistivity drift issues in phase change memory cells.
Implementation Method 1
using pointers in a drift content-addressable memory (CAM) that references entries in the media manager cache
Data Source
AI summary
A method to cache memory requests while accounting for phase change memory cell drift is described. The method includes adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells; adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request; writing the user data of the write memory request to the set of phase change memory cells; and adding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data.