Self-Aligned Phase Change Memory Cell Liner and Electrode Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods of forming memory cells in phase change memory (PCM) face issues such as property changes in the storage element layer due to etching processes, leading to inconsistent properties, misalignment, and etching damage, which affect the scalability and reliability of the memory cells.
Innovation Solution
The storage element layer and top electrode are formed in separate steps after creating a liner layer and surrounding dielectric layer, allowing for a self-aligned process that fixes the position of the storage element layer and protects it from etching damage, thereby resolving overlay shift and etching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the storage element layer is formed using conventional etching processes, then the memory cell can be manufactured, but the storage element layer suffers from property changes, inconsistent properties, and etching damage
Solution Approach 1:
The formation process is segmented into multiple sequential steps: forming the bottom electrode first, then depositing the storage element layer, and finally forming the top electrode. This segmentation allows each layer to be optimized independently, preventing etching damage to the storage element layer while maintaining manufacturing precision.
Solution Approach 2:
The bottom electrode is formed in advance before the storage element layer is deposited. This preliminary action establishes a stable base structure that guides subsequent layer formation, ensuring proper alignment and preventing etching-related property changes in the storage element layer.
2Device complexity
If the storage element layer and top electrode are formed in the same step, then the manufacturing process is simpler, but misalignment and overlay shift issues occur
Solution Approach 1:
The formation of the storage element layer and top electrode is segmented into separate sequential steps rather than a single step. This allows each layer to be precisely aligned with the underlying structure, eliminating overlay shift issues while maintaining reasonable process complexity.
Solution Approach 2:
The storage element layer is formed in advance before the top electrode is deposited. This preliminary action establishes the storage element layer's position and dimensions, providing a reference for subsequent top electrode formation and ensuring accurate alignment.
3Ease of manufacture
If conventional etching processes are used to pattern the storage element layer, then the memory cell structure can be defined, but the storage element layer properties change and become inconsistent
Solution Approach 1:
The harmful etching step is extracted and removed from the storage element layer formation process. Instead of etching the storage element layer to define its pattern, the invention uses direct deposition methods that inherently create the desired pattern without damaging the material properties, thus maintaining composition stability while preserving patterning capability.
Solution Approach 2:
The invention uses a sacrificial dummy structure that is temporarily formed to define the storage element layer pattern during deposition, then removed afterward. This disposable structure enables precise patterning without subjecting the storage element layer to damaging etching processes, maintaining property consistency.
Data Source
AI summary
A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.