PCM In-Memory Convolution Circuit With BJT Selectors
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Solution Overview
Problem
Existing in-memory computation techniques using MOS transistors face scalability issues due to reliability concerns with high intensity write currents and boosted voltages, leading to performance degradation.
Innovation Solution
Utilizing phase-change memory cells and bipolar transistors as cell selectors, with bipolar transistors configured to have a β-gain less than 1, allows for compact and reliable in-memory convolutional computation by limiting current loss and voltage drop through word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MOS transistors are used as cell selectors in resistive memory arrays, then bidirectional current flow capability is achieved, but transistor size must be large to drive high intensity write currents, reducing scalability
Solution Approach 1:
The patent changes the fundamental parameter of current flow directionality by using bipolar transistors with unidirectional current flow instead of MOS transistors with bidirectional current flow. This parameter change allows the use of much smaller transistor sizes while maintaining the required current driving capability for write operations, thus resolving the contradiction between adaptability and device volume.
2Volume of moving object
If MOS transistors are scaled down to reduce size, then device volume decreases, but reliability issues arise due to boosted voltages applied to gate oxide
Solution Approach 1:
The patent changes the transistor type from MOS to bipolar, fundamentally altering the voltage stress mechanism. Bipolar transistors do not require boosted gate voltages like MOS transistors, eliminating the reliability issue associated with gate oxide breakdown. This allows continuous scaling down of transistor size without compromising reliability.
3Productivity
If currents flowing in the same time in a line are summed by Kirchhoff's law, then parallel computation is achieved, but voltage loss in word lines increases, affecting performance
Solution Approach 1:
The patent implements sequential activation of memory cells along each word line, where only one cell is activated at a time. This periodic action transforms the simultaneous current summation (Kirchhoff's law) into a time-sequential process, reducing the instantaneous current and thus minimizing voltage loss in word lines while maintaining parallel computation capability across multiple word lines.
Solution Approach 2:
The bipolar transistors inherently limit the current through their unidirectional conduction特性 and current gain characteristics. This self-limiting behavior reduces the need for external current management circuits, allowing efficient parallel computation with reduced voltage loss without requiring complex additional control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables scalable and resilient in-memory convolutional computation with reduced current loss and voltage drop, supporting both positive and negative weight factors, and overcoming variability in transistor threshold voltage and conductance.
Implementation Method 1
perform convolutional computation using an array comprising a plurality of phase-change memory cells
Implementation Method 2
a plurality of bipolar transistors BJTs used as cell selectors... limiting the loss of voltage in word lines to the current of a single phase-change memory cell
Implementation Method 3
classical in-memory computations are performed by means of a resistive memory array, where each memory point has a resistive value that has been programmed according to the parameters of the calculation
Data Source
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AI summary
The integrated circuit for convolutional computation (CNVL) comprises an array (ARR) of non-volatile memory points (MPTij) each comprising a phase-change resistive memory cell (PCMij) coupled with a bit line (BLj), and a selection bipolar transistor (BJTij) coupled in series with the cell and having a base terminal coupled with a word line (WLi), an input converter circuit (INCVRT) configured to receive and convert input values (A1-A4) to voltage signals (V1-V4) and to successively apply the voltage signals (V1-V4) on selected bit lines (BL1-BL4) over respective time slots (t1-t4), and an output converter circuit (OUTCVRT) configured to integrate over the successive time slots (t1-t4) the read currents (IWL) resulting from the voltage signals (V1-V4) biasing the respective phase-change resistive memory cells (PCMij) and flowing through selected word lines, and to convert the integrated read currents (IWL) to outputs values (Bi).