Phase Change Memory Decoding Architecture Using Low-Voltage Transistors
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Solution Overview
Problem
Existing phase change non-volatile memory devices face limitations in area occupation, energy consumption, and manufacturing costs due to the use of high-voltage CMOS transistors for decoding, and dynamic energy consumption from boosted voltages during programming and reading operations.
Innovation Solution
A decoding architecture for phase change non-volatile memory devices utilizing low-voltage MOS transistors with hierarchical selection switches and protection elements, dynamically biased to reduce voltage stress and achieve desired programming voltages, allowing for efficient selection and biasing of columns and rows during reading and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high-voltage CMOS transistors are used for decoding during programming operations, then the desired programming voltage can be achieved, but area occupation and manufacturing costs increase
Solution Approach 1:
The patent applies dynamics by making the transistor voltage rating adaptive to the operating mode. Low-voltage transistors are used during reading operations, while high-voltage transistors are activated only during programming operations when high voltage is needed. This dynamic switching allows the system to achieve high programming voltage when necessary while minimizing area occupation by using smaller low-voltage transistors for the majority of operations.
Solution Approach 2:
The patent changes the voltage parameter of the transistors based on the operational phase. During reading, low-voltage transistors operate at standard voltages. During programming, the system switches to high-voltage transistors or boosts the voltage temporarily. This parameter change allows achieving high programming voltage requirements while using smaller, lower-cost transistors for normal operations, thereby reducing area occupation and manufacturing costs.
2Use of energy by moving object
If high-voltage CMOS transistors are used for decoding, then programming voltage is achieved, but manufacturing costs increase
Solution Approach 1:
The patent implements dynamic voltage mode switching where the system operates in low-voltage mode during reading (reducing manufacturing requirements) and switches to high-voltage mode only during programming operations. This dynamic approach allows using standard low-voltage transistors for most operations, significantly reducing manufacturing costs while still achieving high programming voltage when needed through temporary voltage boosting or switching to specialized high-voltage transistors only when required.
Solution Approach 2:
The patent changes the voltage operating parameter based on operational needs. By using low-voltage transistors for reading and only activating high-voltage capabilities during programming, the system reduces the overall manufacturing complexity and cost. The parameter change allows the majority of the decoder circuitry to be manufactured with standard low-voltage processes, while high-voltage functionality is added only where absolutely necessary.
3Power
If boosted voltages are applied during programming operations, then programming current is supplied, but dynamic energy consumption increases
Solution Approach 1:
The patent applies periodic action by using boosted voltages only during the specific programming operation cycles rather than continuously. The system switches to high-voltage mode temporarily during programming pulses and returns to low-voltage mode during reading and idle periods. This periodic application of high voltage reduces the average dynamic energy consumption while still providing the necessary programming current when needed.
Solution Approach 2:
The patent dynamically adjusts the voltage level based on the operational phase, using low voltage during reading and high voltage only during programming. This dynamic voltage scaling reduces the dynamic energy consumption by minimizing the time spent in high-power states while ensuring that sufficient programming current is delivered during the brief programming operation windows.
4Area of stationary object
If low-voltage MOS transistors are used with hierarchical selection switches, then area occupation is reduced, but voltage stress management becomes complex
Solution Approach 1:
The patent segments the decoder into hierarchical levels with low-voltage transistors handling fine-grained selection switches and high-voltage paths handling coarse-grained selection and voltage delivery. This segmentation allows low-voltage transistors to be used extensively in the hierarchical selection network (reducing area) while isolating the voltage stress to specific high-voltage paths, making voltage stress management more tractable through clear separation of concerns.
Solution Approach 2:
The patent introduces intermediary high-voltage buffers and protection circuits between the low-voltage hierarchical selection switches and the high-voltage programming paths. These intermediaries isolate the low-voltage transistors from direct voltage stress while enabling them to control high-voltage paths, thus reducing area occupation with low-voltage transistors while managing voltage stress through the intermediary protection layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces area occupation, energy consumption, and manufacturing costs while maintaining high operating speed and performance by using low-voltage transistors, optimizing access times and electrical performance, and enabling competitive performance and cost-effectiveness in phase change non-volatile memory devices.
Implementation Method 1
This electric current, by the Joule effect, generates the temperatures for the phase change.
Implementation Method 2
the characteristics of materials having the property of switching between phases having different electrical characteristics are exploited. These materials may switch between an amorphous, disorderly, phase and a crystalline or polycrystalline, orderly, phase and resistivities of considerably different value
Data Source
AI summary
A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.