Phase Change Memory Stack with Doped Chalcogenide Layers

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Solution Overview

Problem

Phase change memory (PCM) cells used in AI applications face issues with resistance drift, leading to unpredictable resistance changes over time, which affects their thermal stability and scaling behavior, particularly in amorphous phase change materials.

Innovation Solution

The implementation of a semiconductor structure with a stack of undoped and doped chalcogenide layers, including a top electrode and lateral conductive metal layers, which enhances thermal stability and scaling behavior by confining heat and providing a stable current path, thereby reducing resistance drift and improving endurance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If amorphous phase change materials are used for memory operations, then resistance drift occurs leading to unpredictable resistance changes over time, but using crystalline materials or adding projection segments to mitigate drift causes non-linear resistance behavior

Engineering Contradiction:
Improveresistance predictabilityVSAvoidresistance linearity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent employs a composite chalcogenide material structure consisting of Ge2Sb2Te5 (GST) doped with SiO2 and GeSe2. This composite material combines the beneficial properties of different materials: GST provides phase change functionality, SiO2 doping reduces resistance drift by stabilizing the amorphous phase, and GeSe2 addition improves thermal stability. The composite structure achieves both resistance predictability and linear resistance scaling behavior that single-material systems cannot achieve alone.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent systematically varies the doping concentration of SiO2 (ranging from 0 to 20 at%) and GeSe2 (ranging from 0 to 50 at%) to optimize the material properties. By changing these compositional parameters, the invention achieves the desired balance between resistance stability and linearity. The specific parameter optimization shows that controlled doping levels can tune the resistance drift coefficient and thermal stability without sacrificing phase change functionality.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the device is scaled down for higher density AI applications, then thermal stability deteriorates, but maintaining larger device dimensions reduces integration density

Engineering Contradiction:
Improveintegration densityVSAvoidthermal stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The composite chalcogenide material with SiO2 and GeSe2 doping provides enhanced thermal stability that enables device scaling. The SiO2 doping creates a more thermally stable amorphous phase with higher glass transition temperature, while GeSe2 addition further improves thermal properties. This composite approach allows the device to maintain thermal stability even as dimensions are reduced for higher integration density in AI applications.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent optimizes the compositional parameters of the chalcogenide material to achieve thermal stability at scaled dimensions. By adjusting the doping concentrations of SiO2 and GeSe2, the invention tailors the thermal properties of the material to maintain stability during phase transitions even in miniaturized devices. The parameter optimization demonstrates that material composition can be tuned to compensate for the reduced thermal mass in scaled devices.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If projection segments are added to reduce resistance drift, then cycling endurance improves, but device complexity increases

Engineering Contradiction:
Improvecycling enduranceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent achieves improved cycling endurance through compositional parameter changes rather than structural modifications. By doping the chalcogenide material with SiO2 (0-20 at%) and GeSe2 (0-50 at%), the invention enhances the material's resistance to degradation during repeated phase transitions. This approach improves reliability without adding projection segments or other structural elements, thereby avoiding increased device complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in PCM cells with improved thermal stability, scaling behavior, retention, memory window, and reduced resistance drift, enhancing their performance in AI applications.

Implementation Method 1

Heat produced by the passage of an electric current through a heating element, generally made of titanium nitride, can quickly heat and quench the glass

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

Heat produced by the passage of an electric current through a heating element, generally made of titanium nitride, can quickly heat and quench the glass, making it amorphous, or hold it in its crystallization temperature range for some time, thereby switching it to a crystalline state

Methodology Applied
Scientific EffectPhase change: Phase Change

Data Source

PatentUS20230105007A1Artificial intelligence (AI) devices with improved thermal stability and scaling behavior
Publication Date: 2023.04.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20230105007A1 patent drawing
  • US20230105007A1 patent drawing
  • US20230105007A1 patent drawing

AI summary

A phase change memory semiconductor structure includes a substrate; a landing pad located in the substrate; a dielectric located outwardly of the substrate; a heater element located in the substrate outward of the landing pad; a stack including an inner undoped chalcogenide layer outward of the dielectric, a doped chalcogenide layer outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer; and at least one lateral conductive metal layer associated with the stack.