Heterogeneous Memory Controller with Phase-Change and DRAM Modules
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Solution Overview
Problem
Phase-change memory (PCM) systems face significant write latency issues due to the time required to change the state of phase-change material, which hinders performance and efficiency in data storage and retrieval.
Innovation Solution
A memory system and controller architecture that utilizes a combination of phase-change memory modules and faster write-speed memory modules, such as DRAM, to divide data into sub-data and generate non-blocking codes, allowing for concurrent write operations and efficient data reconstruction without blocking read requests, thereby hiding write latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-change memory is used for data storage, then memory persistency is achieved, but write speed deteriorates due to the time required to change the state of phase-change material
Solution Approach 1:
The data is divided into multiple sub-data portions and stored in different memory modules. Some memory modules use phase-change memory for persistency while others use faster memory types for speed-critical operations. This segmentation allows the system to achieve both persistency and high write speed by distributing data across different storage technologies with complementary characteristics.
Solution Approach 2:
A memory controller acts as an intermediary between the CPU and the heterogeneous memory subsystem. It manages data distribution across phase-change memory modules and faster memory modules, handles data reconstruction using erasure coding, and transparently presents a unified interface to applications. This intermediary coordinates the complex interactions between different memory types to achieve both persistency and performance.
2Reliability
If phase-change memory state change is performed for data write, then data storage is achieved, but response time increases due to the slow write process
Solution Approach 1:
The system performs preliminary encoding of data into erasure-coded forms before writing to phase-change memory. This preprocessing allows for faster write operations to the faster memory modules while the phase-change memory writes can proceed asynchronously. The preliminary encoding structure enables rapid data reconstruction without waiting for slow PCM writes to complete, effectively hiding the write latency.
Solution Approach 2:
The memory system maintains continuous useful action by allowing read operations to proceed concurrently with write operations to phase-change memory. The erasure coding structure enables the system to serve read requests from faster memory modules or partially reconstructed data while PCM writes are in progress, ensuring that the system remains productive throughout the write latency period rather than idle.
3Reliability
If data is written to phase-change memory modules, then memory persistency is achieved, but read operations are blocked during write processes
Solution Approach 1:
Data is segmented and distributed across multiple memory modules with different characteristics. Phase-change memory modules provide persistency while faster memory modules handle time-critical read operations. The segmentation allows concurrent read and write operations by directing reads to appropriate memory types based on data availability and access patterns.
Solution Approach 2:
The system changes the operational parameters of different memory modules based on workload requirements. During write-intensive operations, phase-change memory modules operate in async mode with relaxed timing. During read-intensive operations, the system prioritizes faster memory modules. This dynamic parameter adjustment allows the system to optimize response speed while maintaining persistency guarantees.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the response speed of PCM systems by reducing write latency and enabling simultaneous read operations during write processes, while also providing memory persistency without the need for a logging mechanism.
Implementation Method 1
The phase-change memory uses the phase-change material that switches between a crystalline state and an amorphous state, and stores data based on a resistivity difference between the crystalline state and the amorphous state.
Data Source
AI summary
A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.