Phase Change Memory Dummy Cell Array Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase change memory devices experience excessive leakage current in precharge mode, which can lead to cell degradation and exceed standby current values, due to the lack of a controlled discharging path for bit lines.
Innovation Solution
A phase change memory device incorporating a dummy cell array that disconnects the discharging path in precharge mode and activates it in active mode to prevent excessive leakage current, using a column switching unit and PMOS transistors to control the connection between bit lines and global bit lines, thereby maintaining a low voltage level on the bit line and minimizing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional cell array is used without a dedicated discharging path, then the device structure is simple, but excessive leakage current occurs in precharge mode causing cell degradation
Solution Approach 1:
The dummy cell array is designed to serve multiple functions: it acts as a discharge path during precharge mode to control leakage current, and serves as a load during active mode to maintain data integrity. This multi-functionality resolves the contradiction by eliminating the need for separate dedicated circuits while addressing the leakage current problem.
Solution Approach 2:
The dummy cell array acts as an intermediary element between the bit line and ground, providing a controlled discharge path during precharge mode. This intermediary structure enables leakage current control without requiring complex dedicated discharge circuits, thus improving reliability while maintaining reasonable structural simplicity.
2Reliability
If a dummy cell array is added to provide discharging path, then leakage current is controlled, but layout area increases
Solution Approach 1:
The dummy cell array is merged with the main cell array structure, sharing the same layout space and interconnect architecture. By combining the discharge function into the existing cell array rather than adding separate dedicated structures, the patent achieves leakage current control while minimizing the increase in layout area.
3Loss of information
If bit line is kept at high voltage during precharge mode, then data can be stored, but leakage current exceeds standby current values
Solution Approach 1:
The dummy cell array is activated in advance during precharge mode to establish a controlled discharge path before the main operation begins. This preliminary action allows the bit line to be maintained at high voltage for data storage while the dummy cell array prevents excessive leakage current by providing a controlled discharge route, thus resolving the contradiction between data storage and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current during precharge mode, preventing cell degradation and ensuring that the leakage current does not exceed standby current values, while allowing controlled discharging in active mode to maintain data integrity.
Implementation Method 1
The PCM can be crystallized when a low current, i.e., a current less than a threshold value, flows through the PCR 4. As a result, the PCM2 becomes a crystalline phase, that is the PCM 2 becomes a low resistance material. As shown in FIG. 2b, the PCM 2 can be amorphized when a high current, i.e., a current higher than a threshold value, flows through the PCR 4. That is, the temperature of the PCM 2 is increased higher than its melting point when a high current flows through the PCR 4. As a result, the PCM 2 becomes an amorphous phase, that is, the PCM 2 becomes a high resistance material.
Implementation Method 2
Heat is generated when a current flows through the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either the crystalline phase or the amorphous phase depending on the current applied to the upper electrode 1 and the lower electrode 3.
Data Source
AI summary
A phase change memory device includes a cell array having a phase change resistance cell arranged at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a first bit line discharge signal. A column switching unit selectively controls a connection between the bit line and a global bit line in response to a column selecting signal. The dummy cell disconnects a discharging path in response to the first bit line discharge signal in a precharge mode, and discharges the bit line in response to the first bit line discharge signal in an active mode.