Phase Change Memory Lower Electrode Ground Line Spacing
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Solution Overview
Problem
Conventional phase change memory devices face challenges in achieving high integration due to leakage currents caused by a short distance between the lower electrode and the ground line, leading to increased voltage and incorrect sensing of cell states.
Innovation Solution
Increasing the distance between the lower electrode and the ground line by forming larger contact plugs in the isolation structure, which reduces leakage currents and enhances sensing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between the lower electrode and the ground line is reduced to increase integration density, then the integration level is improved, but leakage current increases causing voltage rise and incorrect sensing
Solution Approach 1:
The patent introduces an intermediate structure (isolation structure with contact plugs) between the lower electrode and the ground line. This intermediary element increases the distance between these two components without reducing the overall cell footprint, thereby maintaining integration density while preventing leakage current and ensuring reliable sensing.
2Reliability
If the distance between the lower electrode and the ground line is increased to prevent leakage current, then sensing accuracy is improved, but the unit cell size increases reducing integration
Solution Approach 1:
The patent resolves the spatial conflict by utilizing the vertical dimension through multi-layer stacking. The lower electrode, phase change layer, and upper electrode are arranged in vertical layers, allowing the horizontal distance between the lower electrode and ground line to be increased for reliable sensing while maintaining compact overall cell dimensions through vertical integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for stable ground voltage application and accurate cell state sensing, enabling smaller unit cell sizes and improved integration in phase change memory devices.
Implementation Method 1
a phase change, which occurs in a phase change layer interposed between a lower electrode and an upper electrode, from a crystalline state to an amorphous state is due to current flow between the lower electrode and the upper electrode
Implementation Method 2
the phase change layer undergoes a phase change by heat, that is, Joule heat, between the amorphous state and the crystalline state
Data Source
AI summary
A phase change memory device includes a semiconductor substrate having active regions and an isolation structure; gate lines extending in a direction perpendicular to the active regions; a source region and a drain region formed in a surface of each active region; a dot type lower electrode including a first contact plug formed in the drain region; second contact plugs formed in the source region and the isolation structure forming a line parallel to the gate line; a lower electrode contact formed on the lower electrode; a phase change layer and an upper electrode formed on the lower electrode contact; an upper electrode contact formed on the upper electrode; contacts for ground lines, formed between the active regions to come into contact with the second contact plugs; a bit line formed in the active region; and ground lines formed between the active regions.