Phase Change Memory Top Electrode Uniformity via Nitride Planarization
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Solution Overview
Problem
The existing manufacturing processes for phase change memory structures face challenges such as non-uniformity of top electrode layers due to chemical mechanical polishing, increased electrical resistance between bit lines and vias, and protrusion of vias which can lead to bit line breakage and reduced cell yield.
Innovation Solution
A new process where a continuous metal silicon nitride layer and a partial metal layer are deposited before dividing the memory cells, allowing for a temporary nitride layer to protect the top electrodes during via formation and enabling direct metal-to-metal contact between the bit line and via, reducing resistance and protrusion issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical mechanical polishing is used to planarize the top electrode layers, then the surface flatness is improved, but the top electrode layers become non-uniform due to erosion and material removal
Solution Approach 1:
A planarization layer is deposited over the top electrode layers before via formation, creating a flat surface for subsequent processing without eroding the top electrode layers. This preliminary action prevents the harmful effects of chemical mechanical polishing on the top electrode uniformity while still achieving the required surface flatness for via alignment.
2Ease of manufacture
If a continuous metal silicon nitride layer is deposited over the entire surface including dielectric material, then the manufacturing process is simplified, but the bit line contact to via is impeded and resistance increases
Solution Approach 1:
The metal silicon nitride layer is selectively deposited only in regions where top electrode layers are present, not over the entire surface including dielectric material. This local quality approach ensures that the bit line can make direct metal-to-metal contact with the via while the metal silicon nitride layer provides protection and uniformity where needed on the top electrode layers.
3Reliability
If vias are formed to connect bit lines to memory cells, then the electrical connection is established, but via protrusion occurs leading to bit line breakage and reduced cell yield
Solution Approach 1:
A planarization layer is deposited beforehand to provide a cushioning effect that prevents via protrusion from breaking the bit line. This layer absorbs the mechanical stress and prevents direct contact between the protruding via and the bit line, thereby protecting the bit line from breakage while maintaining electrical connectivity.
4Reliability
If the bit line is deposited to contact both the dielectric material and the via, then the electrical path is established, but the non-flat bottom surface increases manufacturing complexity
Solution Approach 1:
The planarization layer is deposited in advance to create a flat surface, allowing the bit line to be deposited as a uniform layer without requiring a non-flat bottom surface. This preliminary planarization simplifies the bit line structure while maintaining the electrical path continuity through the planarization layer to the via.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform top electrode layers, reduced electrical resistance, and a more stable structure with improved cell yield by preventing erosion and bit line breakage, enhancing the overall quality and reliability of phase change memory arrays.
Implementation Method 1
a metal silicon nitride layer is deposited on a top surface of the top electrode layers
Implementation Method 2
Different physical states of the phase change material have different levels of electrical resistance. For example, one state, such as an amorphous state, can have a high electrical resistance, while another state, such as a crystalline state, can have a low electrical resistance.
Data Source
AI summary
A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) above the phase change material layer. The dielectric material can have a top surface (135) that is higher than a top surface (125) of the top electrode layer. The bit line (140) can have a non-flat bottom surface that contacts the top surface of the dielectric material and protrudes down from the top surface of the dielectric material to a top surface of the memory cell.