Phase Change Memory Bottom Electrode Self-Convergence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for manufacturing phase change memory cells with small electrodes suffer from reliability and yield issues due to variations in critical dimensions caused by lithographic processes, leading to inconsistent current density and electrical integrity problems.
Innovation Solution
A manufacturing process that forms self-converged bottom electrodes by using etch masks with compensating variations, ensuring consistent critical dimensions and electrical integrity across the array, independent of lithographic process variations, through techniques like forming sacrificial layers and anisotropic etching to create uniform voids and align electrode openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lithographic processes are used to form small electrodes, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to variations in critical dimensions
Solution Approach 1:
A mandrel structure is introduced as an intermediary element to define the critical dimensions of the bottom electrode. The mandrel is formed by depositing material conformally on the sidewalls of a via, and its dimensions are determined by the via geometry and deposit thickness rather than direct lithographic patterning. This intermediary structure transfers the dimension control from lithography to deposition processes, improving manufacturing precision while maintaining ease of manufacture.
Solution Approach 2:
The patent replaces direct lithographic patterning (mechanical/optical system) with a deposition-based self-aligned structure formation (chemical/physical system). The critical dimensions are controlled by conformal deposition thickness and via geometry rather than lithographic resolution, substituting the limiting lithographic mechanism with a more precise deposition-controlled mechanism.
2Use of energy by moving object
If electrode size is reduced to minimize reset current, then power consumption is reduced, but reliability deteriorates due to variations in current density
Solution Approach 1:
The via structure serves as a feedback-controlled template that automatically compensates for variations in electrode formation. The conformal deposition on the via sidewalls ensures that the mandrel dimensions are self-regulated by the via geometry, providing negative feedback that prevents excessive variation in critical dimensions. This feedback mechanism ensures consistent current density and reliable operation across all memory cells.
Solution Approach 2:
The patent changes the controlling parameter for electrode dimensions from lithographic feature size to deposition thickness and via dimensions. By controlling the conformal deposition thickness and via geometry, the critical dimensions can be precisely controlled with smaller variations, ensuring consistent current density and reliable reset operation while maintaining small electrode size for low power consumption.
3Use of energy by moving object
If bottom electrode contact area is reduced, then reset current magnitude is reduced, but electrical integrity deteriorates due to contact variations
Solution Approach 1:
The via structure is formed in advance as a precisely controlled template before the bottom electrode is deposited. The via dimensions and position are predetermined, and the conformal deposition automatically creates the mandrel with controlled dimensions. This preliminary action ensures that the electrode contact area is precisely controlled before the actual electrode formation, preventing contact variations that would compromise electrical integrity.
Solution Approach 2:
The via structure acts as an intermediary template that mediates between the lithographic patterning and the final electrode formation. It translates the lithographic pattern into a precisely controlled electrode contact area through conformal deposition, ensuring consistent electrical integrity while maintaining small contact area for low reset current magnitude.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves consistent critical dimensions and improved electrical integrity of bottom electrodes, enhancing the reliability and yield of phase change memory cells by minimizing variations in contact area and current density, thus simplifying data programming and reading.
Implementation Method 1
anisotropic etching to create uniform voids and align electrode openings
Implementation Method 2
Phase change materials, such as chalcogenides, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Implementation Method 3
The change from the amorphous to the crystalline state is generally a lower current operation, requiring a current that is sufficient to raise the phase change material to a level between a phase transition temperature and a melting temperature
Implementation Method 4
The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Data Source
AI summary
An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.