Phase-Change Memory FPGA Logic Block for Faster Programmability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The programmable logic block in field-programmable gate arrays (FPGAs) occupies a large area and reduces operation speed due to parasitic components, limiting its application range and increasing manufacturing costs.
Innovation Solution
A programmable logic block using phase-change memory devices with pull-up and pull-down access transistors, allowing for programming of resistance values to represent logic values of 0 or 1, and connecting basic cells to form logic gates, thereby improving speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switch circuit using SRAM or flip-flop is used for programmable logic block, then the FPGA can be programmed by user, but the area occupied is significantly large and operation speed is reduced due to parasitic components
Solution Approach 1:
The patent changes the fundamental parameter of the memory device from SRAM/flip-flop to phase-change memory (PCM). PCM uses phase transitions (crystalline vs. amorphous states) to store data, enabling programmability with much smaller area and lower parasitic capacitance, thereby resolving the speed limitation while maintaining adaptability
Solution Approach 2:
The patent replaces the electrical switching mechanism of SRAM with the physical phase-change mechanism of PCM. The phase transition material (e.g., GST) undergoes reversible phase changes between crystalline and amorphous states, providing a non-volatile, low-power alternative to volatile SRAM while reducing parasitic effects
2Adaptability or versatility
If a switch circuit using SRAM or flip-flop is used for programmable logic block, then the FPGA can be programmed by user, but the area occupied is significantly large
Solution Approach 1:
The patent changes the memory device type from SRAM to phase-change memory, which has a much smaller cell size. PCM cells can be implemented with simpler structures (e.g., single transistor plus phase-change material), reducing the area per bit significantly compared to SRAM's 6T cell structure
Solution Approach 2:
The patent applies different resistance states (high and low resistance) of the phase-change material to represent logic states, enabling compact memory cells where the functional differentiation is achieved through material property variation rather than increased structural complexity
3Adaptability or versatility
If a switch circuit using SRAM or flip-flop is used for programmable logic block, then the FPGA can be programmed by user, but manufacturing costs are increased
Solution Approach 1:
The patent transitions from volatile SRAM to non-volatile phase-change memory, enabling simpler manufacturing processes without requiring complex refresh circuits or volatile memory fabrication steps. PCM can be integrated using standard semiconductor processes with added phase-change material deposition, reducing overall manufacturing complexity and cost
Solution Approach 2:
The patent extracts the volatile memory component (SRAM) and replaces it with non-volatile phase-change memory, eliminating the need for continuous power supply and refresh operations, thereby simplifying the manufacturing process and reducing associated costs
4Adaptability or versatility
If a switch circuit using SRAM or flip-flop is used for programmable logic block, then the FPGA can be programmed by user, but power consumption is increased
Solution Approach 1:
The patent replaces the electrical switching mechanism of SRAM with the physical phase-change mechanism of PCM. Phase-change memory is non-volatile and consumes power only during writing (phase transition), not during data retention, dramatically reducing static power consumption compared to SRAM which requires continuous refresh
Solution Approach 2:
The patent utilizes periodic phase transitions (crystalline ↔ amorphous) driven by controlled heating pulses. The phase-change material undergoes reversible phase changes only when energy is applied, consuming power selectively during state changes rather than continuously, thereby reducing overall power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces development costs and enhances operational performance by providing a simple structure with a high ON/OFF margin, expanding the application range of reconfigurable LSI circuits and enabling faster operation with lower power consumption.
Implementation Method 1
an up-phase-change memory device connected to the pull-up access transistor; a down-phase-change memory device connected to the up-phase-change memory device
Data Source
AI summary
Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.