Phase Change Memory Interleaving Programming with Dummy Cycles
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Solution Overview
Problem
Phase change memory (PCM) cells experience resistance drift over time, leading to inaccurate cell resistance verification and widened resistance distribution in single cell and page programming, which affects data reliability.
Innovation Solution
The method involves interleaving programming and verification cycles with the insertion of dummy cycles to ensure that memory cells are programmed and verified outside the rapid drift region, using a controller to manage the scheduling and ensure resistance change per unit time is within a threshold, thereby minimizing data unreliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single cell program or page program is performed without dummy cycles, then programming speed is faster, but resistance drift causes inaccurate verification and widened resistance distribution
Solution Approach 1:
The programming process is segmented into multiple time intervals with interleaved programming and verification operations. Dummy cycles are inserted between programming intervals to allow resistance stabilization, dividing the continuous programming process into controlled segments that balance speed and accuracy.
Solution Approach 2:
The method employs periodic programming and verification cycles with regular dummy cycles inserted between them. This periodic structure ensures that resistance drift is consistently managed while maintaining efficient throughput through the interleaved operation pattern.
2Measurement precision
If verification is performed immediately after programming, then verification timing is simpler, but resistance drift during verification causes measurement inaccuracy
Solution Approach 1:
Dummy cycles are performed as preliminary actions between programming and verification to allow resistance stabilization. This preliminary stabilization ensures that when verification occurs, the resistance has settled into a stable state, improving measurement accuracy.
Solution Approach 2:
Dummy cycles act as intermediary operations between programming and verification. These intermediate cycles serve as a buffer that allows the resistance to stabilize without requiring complex real-time monitoring or adjustment during the verification process.
3Reliability
If dummy cycles are inserted between programming intervals, then resistance drift is reduced, but total programming duration increases
Solution Approach 1:
The interleaved programming and verification structure maintains continuous useful action by overlapping operations. While one cell is being verified, another cell can be programmed, ensuring that the system remains productive throughout the process rather than having idle periods.
Solution Approach 2:
The method changes the timing parameters of programming and verification operations to optimize the balance between reliability and productivity. By adjusting the duration and spacing of dummy cycles and interleaved operations, the system achieves resistance stability while maintaining acceptable throughput.
Data Source
AI summary
A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.