Configurable Power Control Module for SoC Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor technologies fail to effectively manage both static and dynamic power consumption in SoC architectures, particularly during normal run modes, leading to increased leakage power and system latency.
Innovation Solution
A configurable power control module that includes a ROM module for storing minimum leakage vectors, a main control unit, a control finite state machine, a programmable control register bank, and a peripheral gating and reset signal generation unit, which allows peripherals to be placed into an absolute minimum power state through a method involving ROM lookup tables, offset counters, and scan chain logic, thereby controlling both static and dynamic power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional power reduction schemes (clock gating, dynamic voltage scaling, power down) are used, then dynamic power consumption is reduced, but static power consumption (leakage power) increases
Solution Approach 1:
The patent pre-calculates and stores Minimum Leakage Vectors (MLVs) for all possible peripheral states in a ROM module before the system operates. When a peripheral needs to be placed in low-power mode, the controller simply retrieves the pre-computed MLV from ROM and applies it, avoiding the need for real-time leakage calculation while achieving minimum leakage state. This preliminary preparation resolves the contradiction by enabling fast transitions to low-power states without sacrificing leakage optimization.
Solution Approach 2:
The patent implements dynamic control of peripheral power states by allowing the system to switch between different MLVs based on operational requirements. The controller can dynamically select which peripherals to place in minimum leakage mode and which to keep active, creating flexible power domains that adapt to system workload. This dynamic approach allows simultaneous reduction of static power through selective peripheral gating while maintaining system functionality.
2Loss of energy
If power supply is shut down to logic domains during standby mode, then leakage current is reduced, but system latency increases due to reprogramming requirements
Solution Approach 1:
The patent pre-calculates Minimum Leakage Vectors for all peripheral combinations and stores them in ROM during system initialization or manufacturing. When transitioning to standby mode, the controller simply retrieves the pre-computed MLV corresponding to the current peripheral state and applies it immediately, avoiding any reprogramming delay. This eliminates the latency penalty while achieving leakage reduction.
Solution Approach 2:
The patent creates a simplified copy of the peripheral control interface through the Power Control Module (PCM), which can directly manipulate peripheral control registers without requiring full reprogramming sequences. The PCM contains copied/replicated control logic that enables fast state transitions by directly writing MLVs to peripheral registers, bypassing the lengthy reprogramming process while maintaining precise control over peripheral power states.
3Loss of energy
If many on-chip analog switches are used for power domain creation, then leakage power is reduced, but device area increases significantly
Solution Approach 1:
The patent implements a universal Power Control Module (PCM) that can control multiple peripherals through a single integrated interface. The PCM contains general-purpose control logic and MLV storage that can be applied to any peripheral type, eliminating the need for dedicated control circuitry for each peripheral. This multi-functional approach reduces the number of control switches required while maintaining the ability to create fine-grained power domains for leakage reduction.
Solution Approach 2:
The patent merges the control of multiple peripherals into unified power domains managed by the PCM. Instead of using separate analog switches for each peripheral, the system combines related peripherals into shared power domains controlled by common control signals from the PCM. This consolidation significantly reduces the total number of analog switches required while still achieving effective leakage power reduction through coordinated domain management.
4Loss of energy
If peripherals are placed in absolute minimum power state, then both static and dynamic power leakage is reduced, but system throughput may be affected
Solution Approach 1:
The patent implements dynamic power management where the system can rapidly transition peripherals between minimum leakage mode and active mode based on workload requirements. The PCM continuously monitors system activity and adjusts peripheral power states in real-time, placing idle peripherals in minimum leakage mode while keeping active peripherals fully operational. This dynamic adaptation allows the system to achieve low power leakage during idle periods without sacrificing throughput during active periods.
Solution Approach 2:
The patent divides the system into independent power domains for each peripheral or group of peripherals, allowing selective placement into minimum leakage mode. The PCM can segment the system such that only the necessary peripherals remain active while others are gated off, achieving proportional power reduction. This segmentation enables the system to maintain high throughput for critical functions while reducing overall power leakage by isolating and gating non-critical peripherals.
Data Source
AI summary
The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.