2D PCM Matrix Configuration for Write Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase Change Memory (PCM) solid-state drives face significant performance disparities between read and write operations due to asymmetric latencies, leading to low write performance and high variability in mixed workloads, with existing solutions like DRAM-based caching being suboptimal due to limited cache size and layout technology constraints.
Innovation Solution
A storage device configuration utilizing a channel controller and phase change memory integrated circuits arranged in sub-channels and sub-banks, employing a matrix configuration to optimize data distribution and access, where data is broken into chunks and buffered before writing, and read in a controlled manner to balance read and write performances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM-based cache is used to coalesce write commands, then write performance is improved, but the cache size is limited and the effect depends on the ratio of DRAM size to total PCM memory space
Solution Approach 1:
The invention segments the PCM memory space into multiple sub-banks (first sub-bank, second sub-bank, etc.) that can be independently accessed. This segmentation allows parallel write operations to different sub-banks, effectively increasing the throughput without requiring additional cache memory. Each sub-bank can receive write commands simultaneously, thereby overcoming the cache size limitation while improving write performance.
Solution Approach 2:
The invention introduces a new dimension of parallelism by organizing PCM ICs into a two-dimensional array structure with multiple sub-channels and sub-banks. This dimensional organization enables concurrent access patterns where write operations can be distributed across multiple sub-banks simultaneously, achieving improved write performance through spatial parallelism rather than temporal caching.
2Productivity
If the number of concurrent write operations per PCM IC is increased, then data block size is increased and number of program cycles is decreased, but layout technology constraints limit the maximum number of concurrent operations
Solution Approach 1:
The invention divides the PCM memory into multiple sub-banks that can be independently accessed. By distributing data blocks across multiple sub-banks, the system effectively increases the usable data block size without requiring each individual PCM IC to support an excessive number of concurrent write operations. This segmentation approach respects layout technology constraints while achieving larger effective data block sizes through parallel access to multiple sub-banks.
Solution Approach 2:
The invention merges multiple sub-banks into a unified addressable memory space from the host perspective. While each sub-bank has limited concurrent write capacity due to layout constraints, the combined capacity of multiple sub-banks provides an effectively larger data block size and higher throughput, achieving the goal of increased data block size without violating individual IC layout limitations.
3Productivity
If page is split to multiple channels and segments are stored to independent channels, then data block size is increased, but the problem of performance difference between read and write is not addressed
Solution Approach 1:
The invention assigns different access patterns and optimization strategies to different sub-banks based on their local characteristics. Some sub-banks can be optimized for write operations while others maintain faster read access, allowing the system to achieve large effective data block sizes through parallel operations while maintaining balanced read/write performance at the overall system level. This local optimization approach addresses both the data block size requirement and the read/write performance balance.
Solution Approach 2:
The invention implements dynamic access patterns where the controller can selectively activate different sub-banks based on whether the operation is read or write-intensive. This dynamic allocation allows the system to optimize for the current workload type, achieving large data block sizes during writes while maintaining fast read performance when needed, thereby balancing the read/write performance difference.
Data Source
AI summary
A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.