PCM Memory Controller Write Cycle ECC Trigger
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Solution Overview
Problem
Phase change memory (PCM) devices face limitations in write cycles and error detection due to the characteristics of their phase changeable materials, leading to increased error probability over time, which existing error correction code mechanisms struggle to address effectively during write and read operations.
Innovation Solution
A memory system with a memory controller that generates a read command for a memory region when the number of successive write commands reaches a predetermined reference value, allowing for timely error detection and correction by performing ECC operations, thereby reducing the interval between error detection and correction operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of write commands for a memory region increases, then the storage capacity is improved, but the probability of error occurrence increases
Solution Approach 1:
The memory controller performs ECC encoding on write data before storing it in the memory device, preparing error correction capabilities in advance. This preliminary action ensures that error correction mechanisms are already in place before errors occur, allowing the system to maintain high storage capacity while preventing error probability from increasing with write cycles.
Solution Approach 2:
The memory controller implements a feedback mechanism that monitors write operations and triggers ECC decoding operations based on write command counts or time intervals. This feedback loop continuously verifies data integrity after writes, enabling the system to detect and correct errors that occur during storage operations, thus maintaining reliability as storage capacity increases.
2Reliability
If ECC decoding operations are performed frequently, then error detection capability is improved, but the operation time is increased
Solution Approach 1:
The memory controller performs ECC decoding operations periodically based on write command counts or time intervals rather than continuously. This periodic action is triggered when the number of write commands reaches a reference value or after a reference time period, ensuring adequate error detection capability while avoiding excessive operation time consumption from overly frequent decoding.
Solution Approach 2:
The memory controller performs ECC decoding operations selectively based on monitored write command counts or time intervals rather than after every single write operation. This partial action approach provides sufficient error detection capability for the storage capacity while preventing excessive operation time by avoiding redundant decoding operations when error probability is low.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.