Phase Change Memory Cell With Junction Selector
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Solution Overview
Problem
Phase change memory devices using chalcogenide materials face issues with current leakage in the amorphous (reset) state, leading to high power consumption due to undesired power consumption when a voltage is applied across the Ovonic Threshold Switch (OTS) in its high resistivity state.
Innovation Solution
The implementation of a phase change memory device with a PN junction diode as the selection element, where the PN junctions are formed using chalcogenic materials with steep rectifying properties, reducing leakage currents by isolating the heater layer with a sheath and spacer layers, and using a compact cell structure with sublithographic dimensions to minimize electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a voltage is applied across the OTS in its high resistivity state, then the memory cell can be read or written, but current leakage occurs leading to high power consumption
Solution Approach 1:
The memory cell is segmented into distinct functional regions: the OTS ( Ovonic Threshold Switch) region for selection and the PCM (Phase Change Memory) region for storage. This segmentation allows the OTS to be optimized for low-leakage selection while the PCM handles storage, reducing overall power consumption by preventing leakage currents from affecting the entire cell structure.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the OTS and the PCM layer. This buffer layer acts as a mediator that electrically isolates the high-resistivity OTS from the PCM, preventing direct leakage paths while still allowing controlled current flow during write operations, thereby reducing standby power consumption.
2Productivity
If the cell dimensions are reduced to increase integration density, then more cells can be packed, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The invention transitions from planar 2D cell structures to a vertically stacked 3D architecture. The OTS, buffer layer, and PCM are stacked in vertical layers, allowing high integration density to be achieved through the third dimension (vertical stacking) rather than by reducing lateral dimensions, thus maintaining manufacturability and dimensional control.
Solution Approach 2:
The structure employs a nested configuration where the OTS is positioned above the PCM layer, with the buffer layer nested between them. This nesting allows multiple functional layers to be integrated in a compact vertical arrangement, achieving high density without requiring extremely precise lateral alignment, thereby easing manufacturing precision requirements.
3Device complexity
If standard decoding circuits are used to simplify the read/write operation, then circuit complexity is reduced, but the selector must have excellent rectifying properties to prevent leakage
Solution Approach 1:
The OTS material composition and structural parameters are optimized to achieve superior rectifying characteristics. By adjusting the chalcogenide alloy composition and the OTS geometric parameters, the device achieves a high on/off ratio and excellent rectifying properties, enabling the use of standard decoding circuits without suffering from leakage issues.
Solution Approach 2:
The invention uses composite chalcogenide materials for the OTS, combining different chalcogenide compounds to achieve both excellent rectifying properties and compatibility with standard manufacturing processes. This composite approach allows optimization of electrical characteristics while maintaining simplicity in the decoding circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces power consumption and leakage currents, allowing for efficient operation with minimal power usage and enabling the use of standard decoding circuits, while maintaining excellent rectifying properties and compact integration.
Implementation Method 1
Phase change can be obtained by locally increasing the temperature. Below 150° C., both the phases are stable. Starting from an amorphous state, and rising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline.
Implementation Method 2
to cause the chalcogenic material to change its state, the heater is formed by a wall structure obtained by depositing a suitable resistive material. Furthermore, the chalcogenic material includes a thin portion extending transversely to the wall structure, so as to obtain a small contact area.
Implementation Method 3
The implementation of a phase change memory device with a PN junction diode as the selection element, where the PN junctions are formed using chalcogenic materials with steep rectifying properties, reducing leakage currents by isolating the heater layer with a sheath and spacer layers
Data Source
AI summary
A memory cell includes a memory element and a selection element coupled to the memory element. The selection element includes a first junction portion, having a first type of conductivity, and a second junction portion, having a second type of conductivity and forming a rectifying junction with the first junction portion. The first junction portion and the second junction portion are made of materials selected in the group consisting of: chalcogenides and conducting polymers.