Phase Change Memory Read Disturbance Control via Snapback Suppression
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Solution Overview
Problem
Phase change memory (PCM) devices experience read disturbance due to the rapid increase in cell current during read operations, which can alter the crystal structure of the phase change material, leading to inaccurate data retrieval.
Innovation Solution
A semiconductor memory device with a control circuit that includes a bitline driver, bitline decoder, wordline decoder, and sense amplifier, which controls the voltage and current flow to minimize the snapback current and stabilize the crystalline state of the memory cell during read operations, using a hierarchical bitline and wordline structure and an annealing driver to provide a stabilizing current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read voltage is applied to the memory cell to read data, then the cell current increases to enable data detection, but the snapback phenomenon causes the cell current to rapidly increase and generate heat that can change the crystal structure of the phase change material
Solution Approach 1:
The patent applies a preliminary negative voltage to the control electrode before applying the read voltage to the main electrode. This preliminary action adjusts the electric field distribution in advance, preventing the snapback phenomenon from occurring during the read operation, thereby maintaining crystal structure stability while enabling data detection
Solution Approach 2:
The patent changes the voltage parameters by applying a negative voltage to the control electrode and adjusting the read voltage on the main electrode. This parameter change modifies the electric field distribution to suppress the snapback phenomenon, allowing data detection without causing harmful current spikes that would alter the crystal structure
2Speed
If the cell current is increased to improve read speed, then the read operation becomes faster, but the generated heat from the large cell current can alter the crystal structure of the phase change material causing read disturbance
Solution Approach 1:
The patent applies a preliminary negative voltage to the control electrode before the read operation to pre-adjust the electric field, preventing snapback and heat generation during the actual read, thus maintaining crystal structure stability while enabling fast read operations
Solution Approach 2:
The control electrode acts as an intermediary that receives a negative voltage to modulate the electric field between the main electrode and the phase change material. This intermediary action suppresses the snapback phenomenon, allowing fast reads without compromising crystal structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the snapback current and minimizes the risk of read disturbance, ensuring accurate data retrieval and maintaining the crystal structure of the phase change material, thereby enhancing the reliability of PCM devices.
Implementation Method 1
A phase change memory (PCM) device using a material having a variable resistance characteristic is being developed. The resistance of the material varies depending on a crystal structure of the material.
Implementation Method 2
a snapback phenomenon (or snapback) occurs after the cell current reaches the threshold current Ith, so that the cell current increases rapidly along a line (1). The reciprocal of a slope of the line (1) corresponds to a turn-on resistance of the phase change material. When the phase change material is in the crystalline state, a relatively large cell current flows after the snapback. Such a large cell current generates heat
Implementation Method 3
Such a large cell current generates heat, and thus the crystal structure of the phase change material may be changed by the generated heat.
Data Source
AI summary
A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.