Phase Change Memory Read Control for Disturb Reduction
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Solution Overview
Problem
Phase change memory (PCM) cells experience read disturb due to unintended voltage differences between bit lines and word lines during read operations, leading to incorrect data retrieval.
Innovation Solution
A control method that dynamically adjusts the voltages applied to bit lines and word lines during a read operation, with distinct voltage stages to prevent read disturb by ensuring the selector switch remains in the correct state, thereby maintaining the storage state of the PCM cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read operation is performed with standard voltage levels, then the read current can be sufficiently large for detection, but the voltage difference between bit lines and word lines causes read disturb and incorrect data retrieval
Solution Approach 1:
The patent applies dynamic voltage control by adjusting the voltage levels on bit lines and word lines during different phases of the read operation. The controller dynamically changes voltage assignments to ensure that during the sensing phase, the selected cell experiences sufficient voltage difference for current detection, while during other phases, voltage levels are adjusted to prevent read disturb on adjacent cells. This dynamic adjustment resolves the contradiction between needing high read current for detection and preventing voltage-induced data corruption.
Solution Approach 2:
The patent changes the voltage parameters (VBL, VWL) applied to bit lines and word lines based on the read operation stage. During the read operation, different voltage combinations are applied: initially one configuration to enable current flow through the selected cell, then switched to another configuration for sensing, and finally adjusted to prevent disturb effects. This parameter changing approach allows the system to achieve both sufficient read current and data integrity by optimizing voltage levels for each operational requirement.
2Measurement precision
If higher voltage difference is applied to ensure sufficient read current, then the read signal can be detected more reliably, but the storage state of the PCM cell is disturbed and data content becomes incorrect
Solution Approach 1:
The patent segments the read operation into distinct phases with different voltage assignments. By dividing the read operation into multiple stages (initial phase, sensing phase, and stabilization phase), each with optimized voltage levels, the system can apply higher voltage difference only when necessary for current detection while using lower voltage levels during other phases to protect the PCM cell storage state. This temporal segmentation resolves the contradiction between needing high voltage for signal detection and maintaining cell stability.
Solution Approach 2:
The patent performs preliminary voltage adjustment before the actual read operation to prepare the bit lines and word lines in appropriate states. By pre-configuring the voltage levels and ensuring proper initial conditions, the system can then apply the necessary voltage difference for a brief sensing period without causing excessive disturb effects. This preliminary preparation allows safe operation at higher voltage differences when needed while preventing storage state corruption.
3Quantity of substance
If standard crossbar memory architecture is used, then high bit density can be achieved with minimum feature size, but sneak current flows through non-selected cells causing read errors
Solution Approach 1:
The patent uses dynamic voltage control on bit lines and word lines to prevent sneak currents in the crossbar architecture. By dynamically adjusting which bit lines and word lines are at high voltage versus low voltage during different read operations, the system ensures that only the selected cell experiences the complete voltage difference needed for current flow, while non-selected cells have balanced voltages that prevent unintended current paths. This dynamic voltage management maintains high bit density while eliminating sneak current problems.
Data Source
AI summary
A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.