Phase Change Memory Readout Circuit Speed and Crosstalk
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Solution Overview
Problem
The existing data readout circuits for phase change memory face challenges such as low readout speed, low reliability, and potential data crosstalk due to parasitic capacitors, which restrict the speed and accuracy of data retrieval and introduce power consumption issues.
Innovation Solution
A data readout circuit that includes a clamp voltage generating circuit, precharge circuit, clamped current generating circuit, clamped current operation circuit, sense amplifier circuit, and discharge circuit, which together enhance the current difference between high and low resistance states, reduce power consumption, and minimize data crosstalk by performing subtraction and multiplication on the clamped current and discharging remaining charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a small readout current is used to avoid Joule heating, then the phase change memory cell state is preserved, but the readout speed is greatly restricted due to parasitic capacitor charging time
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line capacitor to a reference voltage level before the actual readout operation. This pre-charging action prepares the circuit in advance, so that when the readout current is applied, the capacitor is already in an optimal state for rapid voltage transition, thereby achieving fast readout without requiring large current that would cause Joule heating.
Solution Approach 2:
The patent employs dynamics by using a differential readout circuit with complementary bit lines (bit line and complement bit line) that can rapidly switch between states. The circuit dynamically transitions between different voltage states by controlling the phase change memory cell resistance, allowing fast readout signals to be generated without increasing the magnitude of the readout current, thus avoiding Joule heating while maintaining high speed.
2Speed
If a high readout voltage is applied to achieve fast readout, then the readout speed increases, but the breakdown effect occurs due to internal carriers exceeding the threshold voltage
Solution Approach 1:
The patent uses an intermediary approach by introducing a differential readout circuit that compares the voltage on the bit line with the voltage on the complement bit line. Instead of directly measuring a single bit line voltage that could exceed the breakdown threshold, the circuit measures the voltage difference between two complementary lines, keeping individual line voltages within safe ranges while still achieving fast and accurate readout through the differential comparison.
Solution Approach 2:
The patent applies parameter changes by switching between different resistance states of the phase change memory cell (amorphous high-resistance state and crystalline low-resistance state) to represent binary data. By controlling the resistance parameter of the memory cell rather than varying voltage or current magnitudes, the system achieves fast readout through resistance transitions without causing breakdown effects from excessive voltage or current.
3Use of energy by moving object
If the resistance difference between high and low resistance states is low, then the power consumption is reduced, but the readout speed and reliability are significantly restricted
Solution Approach 1:
The patent employs feedback by using a sense amplifier circuit that amplifies the small voltage difference signal from the differential readout circuit. The sense amplifier provides positive feedback to enhance the voltage difference between the bit line and complement bit line, allowing the circuit to reliably detect even small resistance differences in the phase change memory cell. This feedback mechanism enables accurate and fast readout while maintaining low power consumption by working with small resistance differences rather than requiring large resistance contrasts.
4Measurement precision
If the readout current flows through the phase change memory cell, then the data state can be read, but Joule heat generated may change the basic state of the memory cell
Solution Approach 1:
The patent applies the copying principle by creating a complement bit line that is electrically connected in parallel with the main bit line through the phase change memory cell. The complement bit line serves as a copy of the bit line configuration, allowing the circuit to measure the voltage difference between the original and the copy. This differential measurement approach enables accurate detection of the memory cell state using very small currents that generate negligible Joule heat, thus reading data without altering the memory cell's basic state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution increases the speed and reliability of data readout, decreases the misreading window between resistance states, and reduces power consumption while eliminating data crosstalk, thereby improving the overall performance of phase change memory data retrieval.
Implementation Method 1
the current flowing through the phase change memory cell will cause the phase change memory cell to generate Joule heat
Implementation Method 2
utilizing the Joule heat generated by electric pulse or light pulse to realize reversible phase change of phase change memory material between amorphous (high resistance) state and crystalline (low resistance) state
Implementation Method 3
the presence of parasitic capacitor on bit line will meet the above requirements while, at the same time, incur more time for the operation of current (voltage) readout
Data Source
AI summary
A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result. Compared with the prior art, the data readout circuit of phase change memory provided by the present invention can effectively enhance the data readout speed, decrease the misreading window between high resistance state and low resistance state, reduce the crosstalk of data readout, and improve the reliability of data readout.