Phase Change Memory Reference Circuit Segmentation
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Solution Overview
Problem
Existing phase change memory devices face errors in data reading due to differences in current values caused by varying bias voltages and the location of reference circuits relative to memory cells, leading to inaccurate data determination and slow reading speeds.
Innovation Solution
The memory device incorporates a dual memory unit mode where reference currents are generated by reference resistors formed from the same material and process as the memory units, eliminating process variation differences and reducing loading effects, allowing for more accurate data reading and increased speed by locating reference driving circuits within the memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the reference circuit is located in the read/write circuit at the periphery, then the device complexity is reduced, but the reading accuracy deteriorates due to position differences and process variations
Solution Approach 1:
The patent divides the memory array into multiple segments, each with its own local reference circuit. This segmentation allows reference circuits to be positioned close to memory cells while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent introduces a new spatial dimension by placing reference circuits both at the periphery (global reference) and within the memory array (local reference). This multi-dimensional reference circuit arrangement simultaneously achieves low complexity and high accuracy.
2Device complexity
If the read/write circuit is located at the periphery of the column decoding circuit, then the device complexity is simplified, but the reading speed deteriorates due to the loading effect of bit lines
Solution Approach 1:
The patent segments the memory array into multiple blocks with distributed read/write circuits. This reduces the bit line length and loading effect for each segment, improving reading speed while maintaining simplified circuit architecture through modular design.
Solution Approach 2:
The patent adds spatial distribution across multiple memory blocks as a new dimension, allowing read/write circuits to be positioned optimally for both speed and complexity management rather than being confined to a single periphery location.
3Quantity of substance
If a single memory unit mode is used, then the design capacity is maximized, but the reading accuracy deteriorates due to current value variations and bias voltage differences
Solution Approach 1:
The patent merges multiple reference circuits (both global and local) to provide redundant reference currents for comparison. This combination of multiple reference sources maintains high reading accuracy while allowing the memory array to operate in high-capacity single memory unit mode.
Solution Approach 2:
The patent dynamically adjusts reference current parameters based on the operating mode (single memory unit or dual memory unit). By changing reference current magnitude and source selection, the system maintains accuracy across different capacity modes.
4Device complexity
If the reference current is generated by a transistor in the read/write circuit, then the device complexity is reduced, but the manufacturing precision deteriorates due to process variation differences between transistors and memory cells
Solution Approach 1:
The patent uses phase change memory cells to generate reference currents instead of transistors. This ensures that both the reference current source and the memory cells being read have identical process variations, improving manufacturing precision while maintaining simple reference circuit design.
Solution Approach 2:
The patent creates reference currents by copying the exact same phase change memory cell structure and material composition used for data storage. This copying approach ensures identical process variation characteristics between reference and data elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances reading accuracy and speed by ensuring consistent process variations and eliminating loading effects, allowing for precise determination of data '1' or '0' in dual memory unit mode and maximizing design capacity in single memory unit mode.
Implementation Method 1
reference currents are generated by reference resistors formed from the same material and process as the memory units
Implementation Method 2
a phase change memory (PCM), which can change a resistance value of a component by a crystal phase change of the material thereof
Data Source
AI summary
A memory device includes first and second memory arrays, first and second bit line driving circuits, first and second word line driving circuits, a read/write circuit, a controller, and first and second reference driving circuits. The first and second memory arrays include several memory units. The first and second bit line driving circuits are configured to interpret a memory bit address and drive a bit line. The first and second word line driver circuits are configured to interpret the memory word address and drive the word line. The read/write circuit is configured to read, set or reset the memory units. The controller is configured to switch the first and second memory arrays to work in a single memory unit mode or a dual memory unit mode. The first and second reference driving circuits are configured to drive reference rows.