Reset Current Delivery in Phase Change Memory via Dual Mirror Circuits
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Solution Overview
Problem
Reset current delivery in phase change memory (PCM) devices is challenging due to high cell current requirements and high word line and bit line path resistance, limiting the capability of current mirror architectures to deliver sufficient reset current.
Innovation Solution
The implementation of a selection mirror circuit and a reset mirror circuit in PCM devices, where the reset mirror voltage is lower than the selection mirror voltage, facilitates the delivery of a reset current above a current threshold to the memory cells, ensuring effective reset operations without falsely selecting memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a current mirror architecture is used for reset current delivery, then the circuit structure is simplified, but the reset current delivery capability is limited due to high cell current requirements and high word line and bit line path resistance
Solution Approach 1:
The patent divides the reset current delivery function into two separate circuits: a selection mirror circuit for selecting memory cells and a reset mirror circuit for delivering reset current. This segmentation allows each circuit to be optimized independently, with the reset mirror circuit using a lower negative power supply voltage to deliver higher reset current without affecting other cells, thus resolving the contradiction between circuit simplicity and reset current delivery capability
Solution Approach 2:
The patent dynamically switches between different power supply voltages for the negative power supply of the reset mirror circuit. During reset operations, a lower negative voltage is applied to enable higher current delivery, while during normal operations, a higher negative voltage is used to maintain inhibit voltage levels. This dynamic voltage switching allows the system to adapt to different operational requirements and overcome the fixed voltage limitation
2Reliability
If the negative power supply of the reset current mirror is set to the inhibit voltage to avoid false selection, then false selection is prevented, but the reset current delivery capability is limited
Solution Approach 1:
The patent implements dynamic voltage switching where the negative power supply voltage of the reset mirror circuit is changed based on operational mode. During reset operations, a lower negative voltage is applied to enable higher current delivery, while during normal operations, a higher negative voltage is used to maintain inhibit voltage levels. This dynamic adjustment resolves the contradiction by allowing both high current delivery and false selection prevention at different times
Solution Approach 2:
The patent performs preliminary selection of the target memory cell using the selection mirror circuit before applying the reset current. This preliminary action ensures that only the selected cell is affected by the subsequent reset current pulse, preventing false selection while allowing the use of lower negative supply voltages during the reset phase to deliver sufficient current
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AI summary
Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.