Phase Change Memory Cell Seam Location Adjustment
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Solution Overview
Problem
Seams and defects in the dielectric portions of phase change material (PCM)-based memory cells can cause functional failures and reliability issues due to contamination and physical stress, which existing methodologies have not adequately addressed.
Innovation Solution
The design of a PCM-based memory cell with a raised lower electrode, a phase change feature, and a spacer feature, where the dielectric layer is formed to surround the lower electrode rather than the phase change feature, preventing seams from intersecting the phase change material and thus mitigating contamination and stress-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer is formed to surround the phase change feature, then the phase change feature is well protected from contamination and thermal insulation is improved, but seams in the dielectric layer can intersect the phase change feature causing functional failures and reliability issues
Solution Approach 1:
The patent divides the protective dielectric structure into two separate layers: a lower dielectric layer that surrounds the lower electrode and an upper dielectric layer that surrounds the phase change feature. This segmentation ensures that seams form in different locations - specifically in the lower dielectric layer away from the phase change feature - thereby preventing seam-induced contamination and stress from affecting the phase change material while maintaining reliable thermal and chemical protection.
2Use of energy by moving object
If the dielectric layer is formed to surround the phase change feature, then thermal insulation is improved reducing switching current pulse magnitude, but seams in the dielectric portion cause physical stress on the phase change feature
Solution Approach 1:
The patent segments the dielectric protection into two layers: the lower dielectric layer provides thermal insulation to reduce switching current pulse magnitude, while the upper dielectric layer provides contamination protection. By positioning the seam-forming lower dielectric layer away from the phase change feature and using a separate upper dielectric layer for direct surrounding protection, the patent eliminates physical stress on the phase change feature while maintaining energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the deleterious effects of seams on the memory cell's functionality and reliability by preventing contaminants from reaching the phase change feature and minimizing physical stress, thereby enhancing the overall performance and integrity of the memory cell.
Implementation Method 1
it thermally insulates the phase change feature when switching phases, thereby reducing the magnitude of the switching current pulse needed to write to the memory cell
Implementation Method 2
This switching current pulse, in turn, results in ohmic heating in the PCM and induces some or all of the PCM to change phase
Data Source
AI summary
A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.