Phase Change Memory Isolation Using Segmented Dielectric Stress Management
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Solution Overview
Problem
Phase change memory devices using PN diodes face issues with compressive stress from high-density plasma dielectric layers, leading to leakage current, deteriorated transistor driving characteristics, and stacking faults, which compromise electrical reliability due to defects in the crystalline structure of PN diodes.
Innovation Solution
A phase change memory device is designed with a tensile stress applying interlayer dielectric and sidewall spacers that apply compressive stress, preventing stacking faults and improving adhesion to the semiconductor substrate, while using SEG to form single crystal PN diodes with reduced thermal burden and minimized contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick HDP dielectric layer (2,000 Å or more) is deposited to isolate vertical PN diodes, then isolation between PN diodes is improved, but compressive stress causes the interlayer dielectric to lift or peel from the semiconductor substrate, resulting in leakage current
Solution Approach 1:
The interlayer dielectric is segmented into multiple layers: a first interlayer dielectric layer (2,000-3,000 Å thick HDP dielectric) for isolation, and a second interlayer dielectric layer (500-1,000 Å thick BPSG) as a stress relief layer deposited thereon. This segmentation allows the thick isolation layer to function while the additional layer prevents stress-induced peeling.
Solution Approach 2:
The patent uses a composite dielectric structure combining HDP dielectric material and BPSG material. The HDP layer provides excellent isolation properties, while the BPSG layer provides tensile stress to counterbalance the compressive stress from the HDP layer, preventing lifting and peeling.
2Reliability
If HDP dielectric layer is formed over driving transistors in peripheral circuit region, then isolation is improved, but driving characteristics of MOS transistors deteriorate due to compressive stress
Solution Approach 1:
The interlayer dielectric structure is segmented into functional layers: the HDP dielectric layer provides isolation, while the BPSG stress relief layer is deposited thereon to apply tensile stress that counterbalances compressive stress on MOS transistors, preserving driving characteristics.
Solution Approach 2:
A composite structure of HDP dielectric and BPSG is used where the BPSG layer's tensile stress properties compensate for the HDP layer's compressive stress, allowing both isolation and transistor performance to be maintained.
3Ease of operation
If contact holes are etched through tensile stress applying dielectric layer, then access to impurity region is achieved, but stacking faults occur at the interfaces due to loss of lattices on etching surfaces
Solution Approach 1:
A liner layer (50-100 Å thick silicon nitride or silicon oxide) is deposited on the inner wall of contact holes before filling. This preliminary action protects the etched interface and prevents stacking faults during subsequent epitaxial growth by providing a stable surface.
Solution Approach 2:
The liner layer acts as an intermediary between the etched contact hole wall and the epitaxial silicon layer. It prevents direct contact between the damaged etching surface and the growing crystal, thereby preventing stacking faults while still allowing electrical access to the impurity region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents defects and stacking faults, ensuring reliable electrical performance by maintaining the crystalline structure of PN diodes and reducing thermal stress, thereby enhancing the overall reliability and efficiency of the phase change memory device.
Implementation Method 1
a first interlayer dielectric layer formed on the silicon-containing substrate, to apply tensile stress to the silicon-containing substrate
Implementation Method 2
sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a compressive stress applying dielectric layer
Implementation Method 3
The PN diodes may be formed through selective epitaxial growth (SEG) by employing the semiconductor substrate as a seed
Implementation Method 4
the phase or state of the phase change material can be changed between a crystalline state and an amorphous state upon the application of heat thereto
Data Source
AI summary
A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress.