Phase Change Memory Set Algorithm Using Dual Voltage Pulses
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Solution Overview
Problem
Phase change memory devices face reliability issues due to 'set failure mode' caused by high resistance interfaces formed during operation, leading to bit errors and reduced data storage performance.
Innovation Solution
A method and device for operating phase change memory cells using bias arrangements, including a first voltage pulse to establish a lower resistance state and a second higher voltage pulse to overcome set failure, ensuring successful transition to the lower resistance state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher current density pulse is applied to reset the memory cell, then the phase change material transitions to amorphous state, but compositional changes occur leading to high resistance interface formation
Solution Approach 1:
The patent applies parameter changes by carefully controlling the pulse width and amplitude of the reset operation to achieve amorphous state transition while minimizing compositional changes. The reset pulse parameters are optimized to balance the need for reliable state transition with the need to preserve material composition stability.
2Use of energy by moving object
If a lower current operation is used for set, then energy consumption is reduced, but set failure mode occurs due to high resistance interface
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the set operation to detect the current resistance state. This allows the system to determine whether a set operation is actually needed, avoiding unnecessary lower current operations that could lead to set failure while still reducing overall energy consumption when set operations are not required.
Solution Approach 2:
The patent implements feedback by using the read operation results to control subsequent set operations. The system monitors the resistance state and uses this information to decide whether to apply the set voltage pulse, creating a feedback loop that improves set operation reliability by avoiding operations on cells that are already in the desired state.
3Reliability
If multiple voltage pulses are applied to ensure successful set, then set failure is reduced, but operation complexity increases
Solution Approach 1:
The patent applies partial or excessive action by using a single higher voltage pulse (excessive action) for the set operation rather than multiple lower voltage pulses. This approach simplifies the bias arrangement complexity while ensuring successful set operation by applying sufficient voltage in one decisive action rather than multiple incremental actions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and endurance of phase change memory devices by reducing high current operations and enhancing data storage performance by ensuring accurate resistance state transitions.
Implementation Method 1
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Implementation Method 2
application of electrical current at levels suitable for implementation in integrated circuits
Data Source
AI summary
Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.