Phase Change Memory Short Bit Defect Isolation via Blown Operations
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Solution Overview
Problem
Existing semiconductor memory devices face defects such as short bits in three-dimensional memory arrays, which can propagate and disrupt entire memory array stacks, leading to discarding of affected arrays, especially during normal customer operation.
Innovation Solution
Incorporating a sensing amplification circuit on the wordline and bitline sides to detect and identify single wordline and bitline failures, allowing for the identification of single bit failures, and employing a blown operation to convert short bit defects into open bit defects, thereby reducing the impact of defects on memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays are grown in implementation to increase storage capacity, then memory density is improved, but defect impact propagates and disrupts entire memory array stacks
Solution Approach 1:
The memory array is divided into multiple independently manageable stacks. When a short bit defect is detected in one stack, only that specific stack is affected and can be individually masked or retired, while other stacks continue to function normally. This segmentation prevents defect propagation across the entire memory array, allowing the system to maintain higher reliability despite increased memory density.
2Difficulty of detecting and measuring
If sensing amplification circuits are added to detect and identify single wordline and bitline failures, then defect detection capability is improved, but device complexity increases
Solution Approach 1:
Sensing amplification circuits are introduced as intermediary components between the memory cells and the control logic. These amplifiers detect voltage changes on bitlines and wordlines, enabling identification of single bit failures and short bit defects. The intermediaries translate subtle electrical signals into detectable failure conditions without requiring complex control mechanisms.
Solution Approach 2:
The sensing amplification circuits enable the memory array to self-diagnose defects through automated detection of abnormal voltage conditions. When a short bit defect occurs, the amplifiers automatically detect the voltage deviation and trigger masking operations, reducing the need for external intervention or complex error correction algorithms.
3Reliability
If blown operations are performed to convert short bit defects into open bit defects, then reliability is improved by isolating defects, but loss of time occurs due to conversion operations
Solution Approach 1:
During manufacturing or initialization, the system performs preliminary detection of short bit defects using the sensing amplification circuits. Defects are identified and masked before the memory array enters normal operation, preventing future failures. This preliminary action eliminates the need for time-consuming conversion operations during runtime, as defects are addressed proactively.
Solution Approach 2:
When a short bit defect is detected, the system performs a blown operation to convert the short circuit into an open circuit, effectively isolating the defective bit. The defective bit is then discarded from active use through masking, while the rest of the memory array continues to function. This approach recovers the majority of the array's functionality by sacrificing only the minimal defective portion.
Data Source
AI summary
A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.