Phase Change Memory Thermal Insulation for High Integration
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Solution Overview
Problem
High integration of semiconductor memory devices leads to decreased reliability of phase change memory elements in the lowermost and uppermost layers due to reduced heat escaping and increased wiring resistance, limiting the number of memory cells that can be written and stored in the same layer.
Innovation Solution
The use of insulating films with higher thermal insulation properties on the side surfaces of memory cells in the lowermost and uppermost layers, and varying the thickness and material properties of interlayer and insulating films between layers to reduce heat loss and increase write current efficiency, while maintaining high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor memory is formed across multiple layers to achieve high integration, then the memory cell density is improved, but the reliability of PCM elements in the lowermost layer and uppermost layer decreases
Solution Approach 1:
The patent applies different thermal insulation configurations to different locations (lowermost and uppermost layers versus intermediate layers). Heat insulating films are specifically added to the side surfaces of memory cells in the lowermost and uppermost layers, while intermediate layers use conventional interlayer insulating films. This local differentiation resolves the reliability issue at critical layers without compromising the overall high integration benefit.
Solution Approach 2:
The patent segments the insulating structure into two types: conventional interlayer insulating films between intermediate layers, and enhanced heat insulating films at the lowermost and uppermost layers. This segmentation allows targeted improvement of reliability at critical layers while maintaining the high integration architecture across all layers.
2Quantity of substance
If the semiconductor memory is formed across multiple layers to achieve high integration, then the memory cell density is improved, but the reset current required increases
Solution Approach 1:
The patent applies enhanced heat insulation specifically to the lowermost and uppermost layers where heat loss is most problematic, rather than uniformly across all layers. This localized approach reduces the reset current requirement at critical layers while maintaining the energy efficiency benefits of the multi-layer structure overall.
3Quantity of substance
If the semiconductor memory is formed across multiple layers to achieve high integration, then the memory cell density is improved, but the wiring resistance increases
Solution Approach 1:
The patent addresses wiring resistance issues locally at the lowermost and uppermost layers by adding heat insulating films to the side surfaces of memory cells. This reduces parasitic heating and improves current confinement in the wiring structures at these critical layers, thereby reducing the effective wiring resistance without compromising the high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of reset operations by reducing the reset current required, allowing for increased memory cell density and improved performance even in high integration scenarios.
Implementation Method 1
a heat insulating film formed to cover a side surface of the phase change memory element
Data Source
AI summary
A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.