PCM Timing Violation Handling via Activate Command Ignoring
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Solution Overview
Problem
In Phase-Change Memory (PCM) devices operating in synchronous environments, timing violations can occur when issuing commands for asynchronous operations, leading to potential malfunctions and reliability issues, particularly due to the lack of sufficient timing constraints to prevent simultaneous Activate commands from interfering with ongoing read operations.
Innovation Solution
Implementing a timing constraint that allows an Activate command to start and ignores any subsequent Activate commands until a preset time tRC has elapsed, ensuring that only one internal read operation is completed at a time, thereby preventing timing violations and ensuring the correct execution of memory commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple Activate commands are issued simultaneously in a synchronous environment, then command execution speed is improved, but timing violations occur and read reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by setting up a timing constraint mechanism (tRC) in advance that automatically prevents timing violations. The circuit is configured to detect when a previous Activate command has completed its required timing interval, and only then allows subsequent Activate commands to proceed. This pre-established timing control ensures that read operations are never interrupted while maintaining high command execution throughput.
2Reliability
If timing constraints are enforced to prevent simultaneous Activate commands, then read reliability is improved, but command processing delay increases
Solution Approach 1:
The timing constraint mechanism operates autonomously without requiring external intervention or complex control logic. The circuit self-monitors the tRC timing interval and automatically enables or disables the Activate command acceptance based on whether the previous operation has completed its timing requirement. This self-service approach minimizes overhead and processing delay while ensuring reliable read operations.
3Use of energy by moving object
If simultaneous Activate commands are allowed, then current consumption is reduced through parallel operations, but timing violations cause malfunctions
Solution Approach 1:
The patent implements dynamic control of command acceptance based on real-time timing conditions. The circuit continuously monitors whether the tRC interval has elapsed since the previous Activate command and dynamically adjusts its responsiveness to new commands. This dynamic approach allows the system to maximize parallel operation opportunities when timing conditions permit, thereby reducing current consumption, while automatically preventing timing violations that would cause malfunctions.
Data Source
AI summary
A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.