Phase Change Memory Via Protection Using Metal Silicon Nitride
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Solution Overview
Problem
The existing processes for manufacturing phase change memory arrays face challenges such as non-uniformity of electrode layers due to chemical mechanical polishing, increased electrical resistance between bit lines and vias, and protrusion of vias which can lead to breakage of bit lines, resulting in reduced cell yield and operational issues.
Innovation Solution
The new process involves depositing a continuous metal silicon nitride layer and a partial metal layer before dividing the memory cells, allowing for a temporary nitride layer to protect the electrodes during via formation and enabling direct metal-to-metal contact between bit lines and vias, reducing protrusion and ensuring uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical mechanical polishing is used to planarize the substrate, then surface flatness is improved, but electrode layer uniformity deteriorates due to erosion
Solution Approach 1:
A metal cap layer is deposited over the electrode layer before the chemical mechanical polishing process. This cap layer acts as a sacrificial protective layer that prevents the polishing process from eroding the electrode layer, thereby maintaining electrode uniformity while still achieving surface planarization.
Solution Approach 2:
The metal cap layer serves as an intermediary between the polishing process and the electrode layer. It absorbs the mechanical action of polishing, protecting the underlying electrode material from direct contact and erosion, thus preserving electrode layer integrity while enabling surface flattening.
2Reliability
If vias are formed to connect bit lines, then electrical connectivity is improved, but electrical resistance increases at the via-bit line interface
Solution Approach 1:
The via structure is modified by changing the material composition and interface geometry. The metal cap layer extends into the via, creating a larger contact area and improved material compatibility at the via-bit line interface, which reduces contact resistance and enhances electrical connectivity.
3Reliability
If vias protrude to reach bit lines, then electrical contact is improved, but bit line breakage risk increases
Solution Approach 1:
The metal cap layer is deposited in advance to cover and protect the electrode layer and extend into the via region. This preliminary protective layer prevents the via material from directly protruding and contacting the bit line with a sharp edge, thereby reducing stress concentration and the risk of bit line breakage while maintaining electrical contact.
Solution Approach 2:
The metal cap layer acts as a cushioning layer between the via structure and the bit line. It absorbs mechanical stress and prevents direct contact between the rigid via material and the bit line, thereby protecting the bit line from breakage while ensuring electrical connectivity through the via.
4Ease of manufacture
If metal layers are deposited after cell division, then via formation is simplified, but electrode layer uniformity deteriorates
Solution Approach 1:
The metal cap layer is deposited over the electrode layer before the memory cells are divided into individual structures. This preliminary deposition ensures that the electrode layer is uniformly covered and protected across the entire substrate, maintaining electrode uniformity even after subsequent cell division and via formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform electrode layers, reduced electrical resistance, and minimized via protrusion, enhancing the reliability and yield of phase change memory devices by preventing erosion and ensuring consistent operation.
Implementation Method 1
depositing a material layer stack including a phase change material layer, a first electrode layer on the phase change material layer, a metal silicon nitride layer in contact with the first electrode layer
Implementation Method 2
non-uniformity of electrode layers due to chemical mechanical polishing
Implementation Method 3
A metal via is deposited in the via socket
Implementation Method 4
Different physical states of the phase change material have different levels of electrical resistance. For example, one state, such as an amorphous state, can have a high electrical resistance, while another state, such as a crystalline state, can have a low electrical resistance
Data Source
AI summary
A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.