Phase Change Memory Via Plug Fabrication
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Solution Overview
Problem
Phase change memory devices require high write current levels to induce phase changes, limiting integration and increasing susceptibility to defects and etch damage during the fabrication of fine via holes, which complicates the formation of reliable and efficient memory cells.
Innovation Solution
The method involves forming a conductive layer and a conformal insulating layer on a semiconductor substrate, creating a via hole, and using ion beam etching to remove excess phase change material from the upper lip of the via hole, forming a pattern that remains on the bottom surface, and repeating this process to create a reliable via plug without anisotropic etching, thereby reducing defects and maintaining the integrity of the phase change material layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional sputtering deposition is used to form phase change material layer, then deposition process is simple, but step coverage is poor and overhanging region forms around via hole upper edge
Solution Approach 1:
The patent changes the deposition parameters by using atomic layer deposition (ALD) instead of conventional sputtering. ALD provides superior step coverage and conformal deposition on complex three-dimensional structures like via holes, eliminating the overhanging region problem while maintaining processability.
Solution Approach 2:
The patent replaces the physical sputtering mechanism with a chemical vapor deposition mechanism (ALD). This substitution allows for more precise control of material deposition and better conformal coverage on vertical surfaces, resolving the step coverage issue.
2Productivity
If via hole diameter is decreased to enhance integration, then device integration increases, but likelihood of defects such as voids increases
Solution Approach 1:
The patent changes the deposition method to ALD, which provides excellent conformal coverage and uniform thickness even in small via holes. This eliminates void formation and ensures reliable filling while maintaining small via hole dimensions for high integration.
Solution Approach 2:
The patent introduces a multi-step process with intermediate steps including deposition of mandrel material, formation of sacrificial layers, and controlled removal steps. These intermediary steps enable precise control of via hole filling to prevent defects while maintaining small dimensions.
3Loss of substance
If CMP process is used to define phase change material layer, then material loss during CMP is reduced, but anisotropic etching is required which causes etch damage
Solution Approach 1:
The patent extracts and removes the problematic anisotropic etching step from the process. By using ALD for conformal deposition and selective removal of sacrificial materials, the need for aggressive anisotropic etching is eliminated, preventing etch damage to the phase change material.
Solution Approach 2:
The patent uses sacrificial materials (such as oxide layers) that are temporarily deposited and then completely removed. These disposable sacrificial layers enable precise definition of the phase change material without requiring damaging etching processes.
4Reliability
If high write current is applied to induce phase change, then phase change is achieved, but access device size and address line size cannot be reduced
Solution Approach 1:
The patent creates a localized confined structure where the phase change material is precisely positioned within via holes. This local confinement increases the current density at the critical interface region, enabling phase change at lower overall current levels and allowing reduction of access device and address line dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and integration of phase change memory devices by reducing defects and etch damage, allowing for more efficient and uniform filling of small via holes, improving the overall performance and yield of the memory devices.
Implementation Method 1
using ion beam etching to remove excess phase change material from the upper lip of the via hole
Implementation Method 2
When a write current flows through the access device and the bottom electrode, Joule heat (sometimes referred to as I2R heat) is generated at an interface between the phase change material layer and the bottom electrode. The Joule heat tends to transform the phase change material layer into a more amorphous state or a more crystalline state.
Data Source
AI summary
Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.