Phase Change Memory Voltage Generator Clock Pulse Width Control

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Solution Overview

Problem

Phase change memory devices face inefficiencies in charge pumping due to insufficient pulse width of the boosting clock signal, leading to charge loss and degraded performance.

Innovation Solution

A phase change memory device with a voltage generator that produces a modified clock signal with a constant pulse width, ensuring sufficient pulse width for the pump operation, even during low sink current conditions, by comparing a divided voltage to a reference voltage and generating a pump enable signal to maintain consistent operating voltage application.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pump circuit uses a boosting clock signal with constant pulse width to generate operating voltage, then the charge pumping efficiency is improved, but the device complexity increases due to the need for additional clock signal modification circuitry

Engineering Contradiction:
Improvecharge pumping efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by modifying the clock signal pulse width in advance before it reaches the pump circuit. The clock signal is adjusted to have a sufficient pulse width that ensures the pump circuit can complete its charging operation fully, preventing charge loss that would otherwise occur during mode transitions. This pre-modification eliminates the need for complex real-time adjustments during pump operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary element - a clock signal modification circuit - that acts as a mediator between the control system and the pump circuit. This intermediary modifies the clock signal characteristics (pulse width) to ensure proper pump operation without requiring direct complex control of the pump circuit itself, thereby reducing overall system complexity while improving efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the boosting clock signal has insufficient pulse width, then the device complexity is reduced, but charge loss occurs and programming voltage application is degraded

Engineering Contradiction:
Improvedevice complexityVSAvoidcharge loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent prevents charge loss by taking preliminary action - modifying the clock signal pulse width before the pump operation begins. By ensuring the clock signal has sufficient pulse width in advance, the pump circuit is given adequate time to complete its charging function, thereby preventing the charge loss that would occur with insufficient pulse width while avoiding complex real-time control mechanisms.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances charge pumping efficiency by preventing charge loss and maintaining effective programming voltage application to phase change memory cells, thereby improving device performance.

Implementation Method 1

A pump circuit may operate on a power supply voltage to generate a desired operating voltage, which may be higher than the power supply voltage

Methodology Applied
Scientific EffectCharge pump: Pump

Data Source

PatentUS9042167B2Phase change memory
Publication Date: 2015.05.26 SAMSUNG ELECTRONICS CO LTD
  • US9042167B2 patent drawing
  • US9042167B2 patent drawing
  • US9042167B2 patent drawing

AI summary

A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference clock signal, and performing a pump operation on a power supply voltage according to the at least one modified clock signal; and a memory cell array that includes a plurality of phase change memory cells connected between word lines and bit lines. The operating voltage is applied to the memory cell array so as to perform a data access operation.