Phase Change Memory Word Line Flatness and Resistance
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Solution Overview
Problem
Phase change memory devices face issues with increased electrical resistance in word lines due to over-etching and deep trench regions, leading to unstable voltage during read mode and unintended programming of non-selected cells, which degrades access time and reliability.
Innovation Solution
The implementation of phase change memory devices with word lines having substantially flat top surfaces and a specific conductivity type, along with the use of buffer lines and molding layers to improve etch selectivity and reduce electrical resistance, while maintaining integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the P-type semiconductor substrate is etched to form deep trench regions between word lines, then the word lines can be formed with proper spacing, but the deep trench regions cannot be completely filled with isolation layer causing voids or seams
Solution Approach 1:
The patent changes the etching parameters and introduces a planarization process to transform the deep trench structure into a shallower, more fillable structure. By modifying the etching depth and adding a planarization step, the isolation layer can be completely filled without voids or seams, resolving the contradiction between word line formation precision and isolation layer quality.
2Manufacturing precision
If the word lines are over-etched to form cell diodes, then the cell diodes can be properly formed, but the word lines become recessed causing increased electrical resistance
Solution Approach 1:
The patent performs preliminary planarization of the word lines before forming the cell diodes. By flattening the word line surfaces in advance, the subsequent etching process can form cell diodes with proper precision while preventing excessive removal of word line material, thus avoiding increased electrical resistance and maintaining reliability.
3Reliability
If the word lines have high electrical resistance due to over-etching, then the parasitic bipolar transistor operation increases, but this degrades access time and reliability
Solution Approach 1:
The patent introduces an intermediary planarization process between word line formation and cell diode formation. This intermediary step acts as a mediator that prevents excessive etching, maintains word line electrical conductivity, and thereby suppresses parasitic bipolar transistor operation without degrading access time or reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes electrical resistance and suppresses parasitic bipolar transistor operation, enhancing the reliability and access time of phase change memory devices without degrading integration density.
Implementation Method 1
the P-type semiconductor substrate may be over-etched while the first N-type semiconductor layer is etched to form the word lines. This is because the P-type semiconductor substrate may not have an etch selectivity with respect to the first N-type semiconductor layer
Implementation Method 2
phase change memory cells have been proposed instead of the flash memory cells
Data Source
AI summary
Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.