Phase Change Memory Write Buffer for Small Block I/O

The patent segments the write operation into two distinct paths: small block writes (less than 4 KB) are handled separately from large block writes. Small writes are accumulated in a write buffer and processed in batches, while large writes go directly to PCM. This segmentation allows the system to optimize for both small and large write operations, reducing write amplification for small blocks while maintaining efficiency for large blocks.

The patent implements preliminary action by accumulating small writes in a write buffer before processing them. Instead of immediately writing each small block to PCM, the system buffers these writes and processes them in batches when certain conditions are met (buffer full, timeout, or host flush). This preliminary accumulation reduces the number of write operations to PCM, thereby reducing write amplification.

The patent merges multiple small write operations into a single batch operation. Instead of performing separate read-modify-write cycles for each small update, the system accumulates multiple writes in the buffer and processes them together. This merging reduces the total number of read and write operations to PCM, significantly reducing latency while maintaining data correctness through proper buffer management and error correction coding.

The write buffer acts as an intermediary between the host and PCM media. It temporarily holds small writes and manages the timing and batching of writes to PCM. This intermediary layer allows the system to decouple the host's write requests from the actual PCM write operations, enabling optimization of write patterns and reducing latency without compromising data integrity.

The patent implements periodic action by flushing the write buffer to PCM at specific intervals rather than continuously. The flush conditions include: when the buffer is full, when a timeout period expires, when the host issues a flush command, or when power is lost. This periodic flushing reduces the frequency of writes to PCM, thereby extending media lifespan while still maintaining the ability to handle high I/O update frequencies through buffer accumulation.

The patent applies discarding and recovering by temporarily holding write data in the volatile write buffer instead of immediately committing it to PCM. This allows the system to discard individual small writes in favor of batch processing, recovering the benefit of high I/O frequency while minimizing actual writes to PCM media. The buffer is periodically discarded (flushed) to PCM when conditions warrant, optimizing the balance between productivity and lifespan.