Phase Change Memory Write Control Reducing Reset Operations
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Solution Overview
Problem
Conventional phase change memory devices experience increased power consumption and degradation due to a high number of reset and set write operations, leading to deteriorated write characteristics and overlapping read currents between cells.
Innovation Solution
A method for driving a phase change memory device that involves sensing the crystallization state of the phase change resistor, comparing cell data with multi-level data, and applying a write voltage corresponding to a threshold voltage to write a high resistance reset state, thereby reducing the number of reset and set operations and improving write operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write operations are used to write multi-level data to phase change memory cells, then data can be stored in the memory device, but the number of reset and set operations increases, leading to increased power consumption and degradation of write characteristics
Solution Approach 1:
The patent applies preliminary action by performing a reset operation before writing set state data to the phase change memory cell. This pre-reset step ensures the cell is in a known initial state, which stabilizes the write operation and reduces the need for multiple retry operations, thereby improving write reliability without significantly increasing the total number of operations
Solution Approach 2:
The patent implements periodic action through a multi-step write process that alternates between reset and set operations. By periodically switching between these operations in a controlled sequence (reset → set → verify → reset → set), the method achieves stable multi-level data writing while managing the total operation count
2Reliability
If multiple reset and set operations are performed to write multi-level data, then data storage is achieved, but power consumption increases
Solution Approach 1:
The preliminary reset operation prepares the phase change memory cell in a consistent initial state before data writing, ensuring that subsequent set operations are more efficient and require less energy. This pre-conditioning reduces the total energy required for successful data storage
Solution Approach 2:
The patent employs feedback through verification operations that read back the written data to confirm successful storage. This feedback mechanism allows the system to detect write failures early and correct them efficiently, reducing the need for repeated high-energy write operations and thereby lowering overall power consumption
3Productivity
If conventional write methods are used, then data can be written to memory cells, but cell degradation occurs and write characteristics deteriorate over time
Solution Approach 1:
By performing a preliminary reset operation, the method ensures that the phase change material is in a consistent crystalline state before writing, which reduces thermal stress and degradation during subsequent write operations. This protective preliminary step extends the endurance of the phase change resistor while maintaining write speed
Solution Approach 2:
The periodic alternation between reset and set operations with verification steps allows for controlled stress cycling that prevents cumulative degradation. By periodically verifying and correcting writes, the method maintains write speed while extending the operational lifetime of the memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of reset and set operations, enhances the reliability and endurance of the phase change resistor, and maintains initial write conditions, resulting in improved write operation characteristics and cell stability.
Implementation Method 1
the PCM 2 is changed to a crystalline or amorphous state depending on a temperature given to the top electrode 1 and the bottom electrode 3
Implementation Method 2
Heat is generated when current flows between the top electrode 1 and the bottom electrode 3 of the PCR 4 for a given period of time
Data Source
AI summary
A phase change memory device including a phase change resistor senses a crystallization state that is changed according to supplied currents to store data corresponding to the crystallization state. The phase change memory device may receive and store multi-level data. The multi-level data is driven to the phase change memory device by reading cell data of a selected cell. The cell data is compared to multi-level data to be written to the cell. A high resistance reset state is written to the phase change resistor by applying a write voltage that corresponds to a threshold voltage when the cell data is different from the multi-level data. The multi-level data is then written to the phase change resistor by writing and verifying a set state that corresponds to the multi-level data.