Phase Change Memory Write Disturb Remediation
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Solution Overview
Problem
Phase change memory cells experience write disturb phenomena due to heat dissipation from neighboring cells, leading to unreliable state determination and resistivity drift, which complicates read operations and requires remediation to maintain data integrity.
Innovation Solution
A system utilizing hierarchical data structures to detect and manage disruptions by storing user data and parity bits, along with write timestamps and overwrite counts, to determine when remediation is necessary, ensuring efficient read requests and data preservation during high resistivity drift and write disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If writes are performed frequently to memory cells, then data update speed is improved, but write disturb effects cause neighbor memory cell states to become unreliable
Solution Approach 1:
The patent performs preliminary detection of write disturb effects by monitoring physical properties (resistance, capacitance, or time-to-phase-change) of neighbor memory cells before they become unreliable. Write timestamps are recorded and used to predict when remediation should occur, preventing data corruption before it happens. This allows frequent writes to continue while maintaining reliability through proactive intervention.
Solution Approach 2:
The system implements feedback mechanisms by continuously monitoring the physical properties of memory cells and comparing them against thresholds derived from write timestamps and access patterns. When neighbor cells show signs of disturbance, the system feedbacks this information to trigger remediation actions such as rewriting or error correction, thereby maintaining data integrity despite high write frequencies.
2Reliability
If remediation is performed frequently to correct write disturb effects, then data integrity is improved, but read latency increases due to additional access operations
Solution Approach 1:
The patent performs preliminary detection of write disturb effects by monitoring physical properties (resistance, capacitance, or time-to-phase-change) of neighbor memory cells before they become unreliable. Write timestamps are recorded and used to predict when remediation should occur, preventing data corruption before it happens. This allows frequent writes to continue while maintaining reliability through proactive intervention.
Solution Approach 2:
Instead of performing remediation on all memory cells uniformly, the system applies partial action by targeting only those neighbor cells that show signs of disturbance based on monitored physical properties and write patterns. This selective approach corrects data integrity issues while minimizing unnecessary read operations and associated latency penalties.
3Measurement precision
If write timestamps and access patterns are monitored continuously, then detection precision of write disturb effects is improved, but device complexity increases due to additional data structures and processing
Solution Approach 1:
The patent segments the monitoring task by dividing memory cells into aggressor cells (recently written) and neighbor cells (potentially affected). Separate data structures track write timestamps for aggressor cells and physical properties for neighbor cells. This segmentation enables precise detection of write disturb effects while managing complexity through structured organization of monitoring data.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates write disturb effects by efficiently determining when remediation is required, maintaining data integrity and reducing read latency in phase change memory cells, thereby enhancing the reliability and performance of phase change memory systems.
Implementation Method 1
a memory controller may place a variable resistance material of a memory cell (sometimes referred to as phase change memory cells) into a crystalline phase by passing a crystallizing current through the variable resistance material, thus warming the variable resistance material of the memory cell to a temperature wherein a crystalline structure may grow
Implementation Method 2
The memory controller may use a stronger melting current to melt the variable resistance material of the memory cell for subsequent cooling to the amorphous phase
Implementation Method 3
writes to a memory cell may cause a write disturb phenomenon to neighbor memory cells (i.e., memory cells that are directly adjacent to a memory cell that is being written). In particular, writes to a memory cell may dissipate heat/thermal energy to neighbor memory cells
Data Source
AI summary
A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.