PCM Memory Controller for Write Disturbance Refresh Control
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Solution Overview
Problem
Phase-change memory (PCM) devices experience write disturbance due to thermal crosstalk during reset processes, leading to unintended phase transitions and data corruption in adjacent cells, which can eventually cause damage.
Innovation Solution
Implement a write disturbance management scheme using periodic scanning based on write count per memory unit, refreshing adjacent memory units when the flipped bit count exceeds a threshold to mitigate thermal effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reset processes are performed on PCM cells to write data, then write operations can be executed, but thermal crosstalk causes unintended phase transitions and data corruption in adjacent cells
Solution Approach 1:
The patent applies preliminary action by performing a read operation on adjacent memory units before writing to the target memory unit. This preliminary read allows the system to detect and correct potential write disturbance effects before they cause data corruption, thereby maintaining data integrity while enabling continuous write operations. The read operation is performed in advance to prevent the harmful thermal crosstalk from causing unrecoverable damage.
2Productivity
If write operations are frequently performed on memory units, then data can be updated efficiently, but write disturbance accumulates and eventually damages the memory device
Solution Approach 1:
The patent implements feedback by monitoring the write count of each memory unit and using this information to determine when to perform protective read operations on adjacent units. The write count serves as feedback that triggers preventive maintenance actions, allowing the system to balance frequent data updates with device longevity by intervening before write disturbance causes permanent damage.
Solution Approach 2:
By tracking write counts and performing read operations before the write disturbance threshold is reached, the system applies preliminary action to prevent device degradation. This proactive approach allows efficient data updates while extending device lifetime by addressing write disturbance issues before they accumulate to damaging levels.
3Reliability
If periodic scanning and refreshing of adjacent memory units is performed, then write disturbance is mitigated, but additional read operations increase time consumption
Solution Approach 1:
The patent applies partial action by performing read operations selectively on adjacent memory units based on the write count threshold, rather than continuously reading all adjacent units. This approach mitigates write disturbance for high-risk memory units while avoiding unnecessary read operations on low-risk units, thereby maintaining data correctness without excessive time loss.
Solution Approach 2:
The system applies local quality by focusing protective read operations specifically on adjacent memory units that are at risk from write disturbance, rather than uniformly treating all memory units. This targeted approach ensures data correctness for vulnerable units while minimizing the time overhead by avoiding redundant reads on units that do not require protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces data corruption and extends the lifetime of PCM devices by periodically managing and mitigating write disturbances through refreshing at-risk memory units.
Implementation Method 1
the memory cells include phase-change memory (PCM) cells
Implementation Method 2
write disturbance due to thermal crosstalk during reset processes
Data Source
AI summary
In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.