Phase Change Memory Write Pausing for Read Latency
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Solution Overview
Problem
Emerging non-volatile memory technologies like flash and PCM exhibit asymmetric latency for read and write requests, leading to increased contention and effective latency for read requests, which negatively impacts system performance due to slow write operations.
Innovation Solution
Implementing write pausing and pre-empting techniques in phase change memory (PCM) systems, allowing for the interruption and resumption of iterative writes in response to read requests, thereby reducing read latency by prioritizing read operations and minimizing redundant write services.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If iterative write techniques are used to improve write accuracy, then manufacturing precision is improved, but loss of time increases due to multiple read-verify cycles
Solution Approach 1:
The system performs preliminary actions by initiating write operations and preparing verification sequences in advance. The controller starts the iterative write process and begins preparing the verify-read sequence before the write is complete, allowing overlapping execution of write and verification tasks to reduce total time.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that while write operations are executing, the controller continuously prepares verification sequences and manages memory bank scheduling. This prevents idle time between write and verify operations, keeping the system continuously productive.
2Manufacturing precision
If write operations are prioritized to ensure data accuracy, then manufacturing precision is improved, but loss of time increases for read requests due to contention
Solution Approach 1:
The memory system is segmented into multiple independent memory banks that can operate in parallel. The controller can schedule write operations to one bank while simultaneously servicing read requests to other banks, thereby reducing read latency through spatial segmentation and parallel execution.
Solution Approach 2:
The controller dynamically schedules and prioritizes operations based on current system state. It can adjust the timing and allocation of write versus read operations across memory banks, dynamically balancing between ensuring write accuracy and minimizing read latency based on workload conditions.
3Speed
If read requests are prioritized to reduce read latency, then speed is improved, but reliability decreases due to interrupted write operations
Solution Approach 1:
The system performs preliminary actions by initiating write operations and preparing verification sequences in advance. The controller starts the iterative write process and begins preparing the verify-read sequence before the write is complete, allowing overlapping execution of write and verification tasks to reduce total time.
Solution Approach 2:
The iterative write technique incorporates feedback through verify-read operations. The controller reads back written data to verify correctness, and this feedback mechanism ensures that even if writes are interrupted or prioritized differently, data integrity is maintained through verification and potential re-attempts.
4Volume of stationary object
If multiple memory banks are used to increase capacity, then volume is improved, but device complexity increases due to scheduling requirements
Solution Approach 1:
The memory system is segmented into multiple independent memory banks that can operate in parallel. The controller can schedule write operations to one bank while simultaneously servicing read requests to other banks, thereby reducing read latency through spatial segmentation and parallel execution.
Solution Approach 2:
Each memory bank operates with a degree of independence, managing its own internal state and operations. This self-service capability reduces the burden on the controller, as banks can autonomously handle certain operations without requiring complex centralized coordination for every task.
Data Source
AI summary
Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.