Phase Change Memory Write Set Operation Voltage Control Circuit

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Solution Overview

Problem

Phase change memory devices face challenges in successfully completing set operations due to clamp conditions caused by transistors, which prevent the desired current versus time profile needed to heat the memory cell for resistance state changes.

Innovation Solution

A voltage control circuit, either with a capacitor or a voltage driver, is implemented to moderate the voltages on the bit and word lines during a write operation, preventing the clamp condition by ensuring the voltage on one terminal increases while the current source provides a ramp down current, thus maintaining the desired voltage range and ensuring successful phase changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a current source provides ramp down current to the memory cell, then the memory cell can undergo phase change, but the transistor clamp condition prevents the desired current versus time profile from being achieved

Engineering Contradiction:
Improveset operation successVSAvoidcurrent versus time profile control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

A voltage control circuit is introduced as an intermediary between the current source and the memory cell. This circuit includes a first voltage source connected to the word line and a second voltage source connected to the bit line, allowing independent voltage control to overcome the transistor clamp condition and achieve the desired current profile for reliable set operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the voltage parameters on the word line and bit line independently during the write operation. By dynamically adjusting the voltage sources rather than relying solely on current control, the system can maintain the memory cell voltage within the required range despite transistor clamp effects, enabling successful phase change

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the voltage on the bit line is allowed to decrease during set operation, then the current source can provide ramp down current, but the transistor enters clamp condition and prevents successful set operation

Engineering Contradiction:
Improvewrite operation speedVSAvoidset operation completion
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The voltage control circuit performs preliminary action by pre-establishing appropriate voltage levels on the word line and bit line before the current ramp down begins. This ensures that when the current decreases, the voltage remains within the range needed to prevent transistor clamping, allowing the set operation to complete successfully without compromising write speed

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The voltage control circuit effectively counteracts the decrease in voltage output from the current source, allowing for successful completion of set operations by maintaining the voltage within the required range, thereby ensuring accurate resistance state changes in phase change memory cells.

Implementation Method 1

accumulating charge in a capacitor connected to the selected bit line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

providing a ramp down current through a selected memory cell... needed to heat the memory cell for resistance state changes

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS10373682B2Write set operation for memory device with bit line capacitor drive
Publication Date: 2019.08.06 SANDISK TECHNOLOGIES LLC
  • US10373682B2 patent drawing
  • US10373682B2 patent drawing
  • US10373682B2 patent drawing

AI summary

Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.