Phase Change Memory Writing Circuit with Verification Feedback
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Solution Overview
Problem
Phase change memory systems face challenges in maintaining optimal write and read speeds due to drift in current-resistance characteristics, requiring adjustments in writing currents to ensure normal operation, which affects data storage reliability and efficiency.
Innovation Solution
A writing system and method that incorporates a first and second phase change memory cell, a first writing circuit, and a verifying circuit to adjust writing currents based on verification procedures, using different transistors with varying W/L ratios for writing and reading to optimize current output and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If writing current is increased to improve write speed, then write speed is improved, but current-resistance characteristic drift increases affecting reliability
Solution Approach 1:
The patent implements a feedback mechanism where a verifying circuit monitors the resistance of the phase change memory cell after writing operations. The verifying circuit compares the actual resistance with expected values and generates feedback signals to adjust the writing current dynamically. This closed-loop control ensures write speed is maintained while preventing excessive current that would cause characteristic drift and reliability issues.
Solution Approach 2:
The patent makes the writing current dynamic rather than fixed. The writing current is adjusted in real-time based on verification results and drift detection. The system transitions from static current levels to dynamic current adjustment, allowing optimal write speed while adapting to changing memory cell characteristics over time and temperature conditions.
2Reliability
If verification procedures are added to adjust writing currents, then data storage reliability is improved, but processing time increases
Solution Approach 1:
The patent performs verification operations in parallel with subsequent writing operations. Instead of completing all writes then verifying, the system verifies early and adjusts current proactively. The verifying circuit continuously monitors memory cells and prepares adjustment signals before the next write operation, reducing idle time and preventing rework.
Solution Approach 2:
The verification and current adjustment process is integrated continuously into the writing operation rather than being a separate batch process. The verifying circuit operates concurrently, and current adjustments are applied dynamically during ongoing operations. This continuous feedback loop eliminates idle verification phases and maintains productive action throughout the writing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the write speed while maintaining read speed, reducing processing time and improving data storage reliability by dynamically adjusting writing currents based on verification results, thus addressing the drift in current-resistance characteristics.
Implementation Method 1
the phase change memory is heated. The phase change memory may thus be crystallized or melted based on different currents
Implementation Method 2
According to Ohm-Joule's Law, when the current is input to the phase change memory, the phase change memory is heated
Data Source
AI summary
An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.