Phase Change Memory Cell with Precharge Circuit for Read Speed
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Solution Overview
Problem
Conventional phase change memory devices face challenges in achieving high-speed read operations due to diffusion layer capacitance effects and large cell sizes, particularly when using diodes as select switches, which lead to reduced read speeds and increased cell size requirements.
Innovation Solution
A phase change memory device with a select transistor in a diffusion layer and a precharge circuit that precharges non-selected diffusion layers to a predetermined voltage, reducing the influence of diffusion layer capacitance and allowing for high-density memory cell arrangement while maintaining sufficient write current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a diode is used as a select switch for the phase change element, then the cell size can be reduced, but the diffusion layer capacitance causes read speed to decrease
Solution Approach 1:
The precharge circuit performs preliminary action by precharging the diffusion layer to a predetermined voltage before the read operation. This preliminary charging eliminates the capacitance effect during reading, allowing fast read speed while maintaining the small cell size achieved by using diodes as select switches.
2Productivity
If multiple memory cells are written simultaneously on the same word line, then productivity increases, but current concentration on the word line causes potential rise and write current reduction
Solution Approach 1:
The invention extracts the current path from the word line by introducing a ground line as a separate current return path. The select transistor controls current flow to the ground line instead of relying on the word line as the current return path, preventing potential rise and enabling simultaneous writing to multiple memory cells without write current reduction.
3Power
If the select transistor has a large gate width to flow sufficient write current, then write capability is maintained, but the diffusion layer capacitance increases and read speed decreases
Solution Approach 1:
The precharge circuit performs preliminary charging of the diffusion layer to a predetermined voltage before read operations. This eliminates the adverse effect of diffusion layer capacitance during reading, allowing the select transistor to have a sufficiently large gate width for maintaining write current capability without compromising read speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed read operations by minimizing the impact of diffusion layer capacitance and allowing for dense memory cell packing, while ensuring sufficient write current flow, thus improving read speed and reducing cell size.
Implementation Method 1
the diffusion layer capacitance below a non-selected memory cell connected to a non-selected word line can be suppressed by precharging the diffusion layer to a predetermined voltage
Implementation Method 2
a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate
Implementation Method 3
a phase change element for rewritably storing data by changing a resistance state; in a write operation of the phase change memory device, joule heat due to current is generated so as to change the resistance state of the phase change element
Data Source
AI summary
A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.