Phase Change Memory Vertical LED SiC Conductive Region
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Solution Overview
Problem
Conventional phase change memories with silicon-based PN junctions in vertical LEDs experience high drain current due to electrical field carrier formation, hindering density and power consumption improvements, and often have malfunctioning peripheral circuit regions.
Innovation Solution
The implementation of phase change memory with vertical LEDs featuring N-type conductive regions containing SiC, which reduces drain current and enhances current efficiency, along with a peripheral circuit region design that includes MOS transistors and shallow trench isolation units, allowing the peripheral circuit to function correctly without impacting the phase change memory's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon-based PN junctions are used in vertical LEDs, then the phase change memory can be fabricated with conventional materials, but high drain current is generated due to electrical field carrier formation
Solution Approach 1:
The patent changes the material composition parameter of the N-type conductive region from pure silicon to silicon carbide (SiC) containing material. This parameter change fundamentally alters the electrical properties, reducing carrier concentration and drain current while maintaining the vertical LED structure and fabrication process compatibility.
Solution Approach 2:
The patent employs composite material strategy by using silicon carbide (SiC) in the N-type conductive region instead of pure silicon. This composite approach combines the benefits of silicon-based fabrication compatibility with the superior electrical properties of SiC, specifically lower drain current due to wider bandgap and reduced carrier generation.
2Loss of energy
If vertical LEDs with high current efficiency are implemented, then power consumption is reduced, but device complexity increases due to SiC integration
Solution Approach 1:
By changing the material parameter to SiC-containing composition in the N-type region, the patent achieves lower power consumption through reduced drain current. The same parameter change is applied to the P-type region with Si-containing material, creating a heterostructure that improves efficiency while maintaining manufacturing feasibility.
Solution Approach 2:
The patent applies local quality principle by introducing SiC specifically in the N-type conductive region where carrier generation and drain current are most problematic, while using conventional Si in the P-type region. This localized material optimization reduces overall power consumption without requiring complete restructuring of the entire device.
3Productivity
If peripheral circuit region is integrated on the same substrate, then device density is improved, but the peripheral circuit often malfunctions due to interference with phase change memory
Solution Approach 1:
The patent segments the substrate into distinct storage region and peripheral circuit region, allowing independent optimization of each area. The storage region uses vertical LEDs with SiC-based conductive regions for phase change memory, while the peripheral circuit region uses conventional CMOS technology, enabling both high density and reliable circuit operation without mutual interference.
Solution Approach 2:
The patent applies different material compositions and structural optimizations to different regions: SiC-containing conductive regions in the storage area for low-power phase change operation, and conventional silicon-based structures in the peripheral circuit area for reliable logic operation, achieving both high density and functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of SiC in N-type conductive regions decreases drain current through vertical LEDs, increasing their efficiency, and the optimized peripheral circuit region design ensures proper functionality without affecting the phase change memory's performance, achieving high density and low power consumption.
Implementation Method 1
high drain current due to electrical field carrier formation
Implementation Method 2
N-type conductive regions containing SiC, which reduces drain current
Implementation Method 3
Heat is supplied for phase change of phase change material. According to the supplied heat, the phase change material has two stable phases, for example non-crystal phase and crystal phase
Implementation Method 4
Heat is supplied for phase change of phase change material
Implementation Method 5
When the phase change material is heated at the proximity of melted temperature for a short time and then is cooled rapidly, it may phase change from crystal phase to non-crystal phase
Implementation Method 6
when the phase change material is heated below the melted temperature for a long time and then is cooled slowly, it may phase change from non-crystal phase to crystal phase
Data Source
AI summary
The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.